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Pipelined Datapath The MIPS Example 2018/11/29

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Presentation on theme: "Pipelined Datapath The MIPS Example 2018/11/29"— Presentation transcript:

1 Pipelined Datapath The MIPS Example 2018/11/29
\course\cpeg323-05F\Topic6a-323.ppt

2 The single-cycle datapath
2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

3 Instructions being executed using the single-cycle datapath, assuming pipelined execution.
2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

4 The pipelined version of the datapath.
2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

5 IF and ID: the first pipe stage of an instruction, with the active
portions of the datapath highlighted. 2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

6 IF and ID: the first pipe stage of an instruction, with the active
portions of the datapath highlighted. 2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

7 EX: the third pipe stage of a load instruction, highlighting
the portions of the datapath used in this pipe stage. 2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

8 MEM: the fourth pipe stage of a load instruction,
highlighting the portions of the datapath used in this pipe stage. 2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

9 WB: the fifth stage of a load instruction,
highlighting the portions of the datapath used in this pipe stage. 2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

10 The third pipe stage of a store instruction
2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

11 MEM : the fourth pipe state of a store instruction.
2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

12 The fifth pipe stage of a store instruction.
Guang R Gao: nothing happens here The fifth pipe stage of a store instruction. 2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

13 The pipelined version of the datapath.
Can you find a problem even if there are no dependencies? What instructions can we execute to manifest the problem? 2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

14 The corrected pipelined datapath to properly
Guang R Gao: which inst supplies the destination R ? At which stage ? The corrected pipelined datapath to properly handle the load instruction. 2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

15 The portion of the datapath that is used in all five
stages of a load instruction. 2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

16 Single-cycle pipeline diagrams for clock cycles 1.
Guang R Gao: This style shows a snapshot of all instructions in execution within the pipeline Single-cycle pipeline diagrams for clock cycles 1. 2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

17 Single-cycle pipeline diagrams for clock cycles 2.
2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

18 Single-cycle pipeline diagrams for clock cycles 3.
2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

19 Single-cycle pipeline diagrams for clock cycles 4.
2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

20 Single-cycle pipeline diagrams for clock cycles 5.
2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

21 Single-cycle pipeline diagrams for clock cycles 6.
2018/11/29 \course\cpeg323-05F\Topic6a-323.ppt

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