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Introduction to Intel IA-32 and IA-64 Instruction Set Architectures

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Presentation on theme: "Introduction to Intel IA-32 and IA-64 Instruction Set Architectures"— Presentation transcript:

1 Introduction to Intel IA-32 and IA-64 Instruction Set Architectures

2 Dr. Alexey Lugovskoy will be giving a presentation at 4pm this Thursday
(Feb 21) in 499 Dirac. After the presentation there will be a brief discussion about the new undergraduate computational biology degree at FSU and Dr. Lugovskoy will answer questions regarding opportunities for employment in this field. Refreshments and pizza will also be provided.

3 History 11/29/2018 9/27/2007 11:23:26 PM week06-3.ppt
CDA3100 week06-3.ppt

4 Recent Intel Processors
11/29/2018 Recent Intel Processors The Intel® Pentium® 4 Processor Family ( ) The Intel® Xeon® Processor ( ) The Intel® Pentium® M Processor (2003-Current) The Intel® Pentium® Processor Extreme Edition ( ) The Intel® Core™ Duo and Intel® Core™ Solo Processors (2006-Current) The Intel® Xeon® Processor 5100 Series and Intel® Core™2 Processor Family (2006-Current) 9/27/ :23:26 PM week06-3.ppt CDA3100 week06-3.ppt

5 History 11/29/2018 9/27/2007 11:23:27 PM week06-3.ppt
CDA3100 week06-3.ppt

6 Most Recent Intel Processors
11/29/2018 Most Recent Intel Processors 9/27/ :23:27 PM week06-3.ppt CDA3100 week06-3.ppt

7 Intel Core 2 Duo Processors
11/29/2018 Intel Core 2 Duo Processors 9/27/ :23:28 PM week06-3.ppt CDA3100 week06-3.ppt

8 Intel Core 2 Quad Processors
11/29/2018 Intel Core 2 Quad Processors 9/27/ :23:28 PM week06-3.ppt CDA3100 week06-3.ppt

9 Bit and Byte Ordering 11/29/2018 9/27/2007 11:23:29 PM week06-3.ppt
CDA3100 week06-3.ppt

10 Intel Assembly Each instruction is represented by
11/29/2018 Intel Assembly Each instruction is represented by Where label presents the line A mnemonic is a reserved name for a class of instruction opcodes which have the same function. The operands argument1, argument2, and argument3 are optional. There may be from zero to three operands, depending on the instruction 9/27/ :23:29 PM week06-3.ppt CDA3100 week06-3.ppt

11 Memory Modes 11/29/2018 9/27/2007 11:23:30 PM week06-3.ppt
CDA3100 week06-3.ppt

12 Addressing The processors use byte addressing
11/29/2018 Addressing The processors use byte addressing Intel processors support segmented addressing Each address is specified by a segment register and byte address within the segment 9/27/ :23:30 PM week06-3.ppt CDA3100 week06-3.ppt

13 11/29/2018 9/27/ :23:30 PM week06-3.ppt CDA3100 week06-3.ppt

14 Intel Registers 11/29/2018 9/27/2007 11:23:31 PM week06-3.ppt
CDA3100 week06-3.ppt

15 Basic Program Execution Registers
11/29/2018 Basic Program Execution Registers General purpose registers There are eight registers (note that they are not quite general purpose as some instructions assume certain registers) Segment registers They define up to six segment selectors EIP register – Effective instruction pointer EFLAGS – Program status and control register 9/27/ :23:31 PM week06-3.ppt CDA3100 week06-3.ppt

16 General Purpose and Segment Registers
11/29/2018 General Purpose and Segment Registers 9/27/ :23:32 PM week06-3.ppt CDA3100 week06-3.ppt

17 General Purpose Registers
11/29/2018 General Purpose Registers EAX — Accumulator for operands and results data EBX — Pointer to data in the DS segment ECX — Counter for string and loop operations EDX — I/O pointer ESI — Pointer to data in the segment pointed to by the DS register; source pointer for string operations EDI — Pointer to data (or destination) in the segment pointed to by the ES register; destination pointer for string operations ESP — Stack pointer (in the SS segment) EBP — Pointer to data on the stack (in the SS segment) CDA3100 week06-3.ppt

18 Alternative General Purpose Register Names
11/29/2018 Alternative General Purpose Register Names CDA3100 week06-3.ppt

19 11/29/2018 Registers in IA-64 CDA3100 week06-3.ppt

20 11/29/2018 Segment Registers CDA3100 week06-3.ppt

21 Operand Addressing Immediate addressing Register addressing
11/29/2018 Operand Addressing Immediate addressing Maximum value allowed varies among instructions and it can be 8-bit, 16-bit, or 32-bit Register addressing Register addressing depends on the mode (IA-32 or IA-64) CDA3100 week06-3.ppt

22 11/29/2018 Register Addressing CDA3100 week06-3.ppt

23 Memory Operand Memory operand is specified by a segment and offset
11/29/2018 Memory Operand Memory operand is specified by a segment and offset CDA3100 week06-3.ppt

24 Offset Displacement - An 8-, 16-, or 32-bit value.
11/29/2018 Offset Displacement - An 8-, 16-, or 32-bit value. Base - The value in a general-purpose register. Index — The value in a general-purpose register. Scale factor — A value of 2, 4, or 8 that is multiplied by the index value. CDA3100 week06-3.ppt

25 11/29/2018 Effective Address CDA3100 week06-3.ppt

26 Effective Address Common combinations Displacement Base
11/29/2018 Effective Address Common combinations Displacement Base Base + displacement (Index * scale) + displacement Base + index + displacement Base + (Index * scale) + displacement CDA3100 week06-3.ppt

27 Addressing Mode Encoding
11/29/2018 Addressing Mode Encoding CDA3100 week06-3.ppt

28 Fundamental Data Types
11/29/2018 Fundamental Data Types CDA3100 week06-3.ppt

29 11/29/2018 Example CDA3100 week06-3.ppt

30 Pointer Data Types Near pointer Far pointer 11/29/2018
CDA3100 week06-3.ppt

31 11/29/2018 128-Bit SIMD Data Types CDA3100 week06-3.ppt

32 11/29/2018 BCD Integers Intel also supports BCD integers, where each digit (0-9) is represented by 4 bits CDA3100 week06-3.ppt

33 Floating Point Numbers
11/29/2018 Floating Point Numbers CDA3100 week06-3.ppt

34 General Purpose Instructions
11/29/2018 General Purpose Instructions Data transfer instructions CDA3100 week06-3.ppt

35 Data Transfer Instructions
11/29/2018 Data Transfer Instructions CDA3100 week06-3.ppt

36 Data Transfer Instructions
11/29/2018 Data Transfer Instructions CDA3100 week06-3.ppt

37 Binary Arithmetic Instructions
11/29/2018 Binary Arithmetic Instructions CDA3100 week06-3.ppt

38 Decimal Arithmetic Instructions
11/29/2018 Decimal Arithmetic Instructions CDA3100 week06-3.ppt

39 11/29/2018 Logical Instructions CDA3100 week06-3.ppt

40 Shift and Rotate Instructions
11/29/2018 Shift and Rotate Instructions CDA3100 week06-3.ppt

41 Bit and Byte Instructions
11/29/2018 Bit and Byte Instructions CDA3100 week06-3.ppt

42 Bit and Byte Instructions
11/29/2018 Bit and Byte Instructions CDA3100 week06-3.ppt

43 Control Transfer Instructions
11/29/2018 Control Transfer Instructions CDA3100 week06-3.ppt

44 11/29/2018 CDA3100 week06-3.ppt

45 11/29/2018 String Instructions CDA3100 week06-3.ppt

46 11/29/2018 I/O Instructions These instructions move data between the processor’s I/O ports and a register or memory CDA3100 week06-3.ppt

47 Enter and Leave Instructions
11/29/2018 Enter and Leave Instructions These instructions provide machine-language support for procedure calls in block structured languages CDA3100 week06-3.ppt

48 Segment Register Instructions
11/29/2018 Segment Register Instructions The segment register instructions allow far pointers (segment addresses) to be loaded into the segment registers CDA3100 week06-3.ppt

49 11/29/2018 Procedure Call Types The processor supports procedure calls in the following two different ways: CALL and RET instructions. ENTER and LEAVE instructions, in conjunction with the CALL and RET instructions CDA3100 week06-3.ppt

50 11/29/2018 Stack CDA3100 week06-3.ppt

51 Calling Procedures Using CALL and RET
11/29/2018 Calling Procedures Using CALL and RET Near call (within the current code segment) Near return CDA3100 week06-3.ppt

52 Far Call and Far Return Far call Far return 11/29/2018
CDA3100 week06-3.ppt

53 Stack During Call and Return
11/29/2018 Stack During Call and Return CDA3100 week06-3.ppt

54 Parameter Passing Passing parameters on the stack
11/29/2018 Parameter Passing Passing parameters through the general-purpose registers Can pass up to six parameters by copying the parameters to the general-purpose registers Passing parameters on the stack Stack can be used to pass a large number of parameters and also return a large number of values Passing parameters in an argument list Place the parameters in an argument list A pointer to the argument list can then be passed to the called procedure CDA3100 week06-3.ppt

55 Saving Procedure State Information
11/29/2018 Saving Procedure State Information The processor does not save general purpose registers A calling procedure should explicitly save the values in any of the general-purpose registers that it will need when it resumes execution after a return One can use PUSHA and POPA to save and restore all the general purpose registers (except ESP) CDA3100 week06-3.ppt

56 Calls to Other Privilege Levels
11/29/2018 Calls to Other Privilege Levels CDA3100 week06-3.ppt

57 Stack For Calling and Called Procedure
11/29/2018 Stack For Calling and Called Procedure CDA3100 week06-3.ppt

58 Procedure Calls For Block-structured Languages
11/29/2018 Procedure Calls For Block-structured Languages ENTER and LEAVE instructions automatically create and release, respectively, stack frames for called procedures The ENTER instruction creates a stack frame compatible with the scope rules typically used in block-structured languages The LEAVE instruction, which does not have any operands, reverses the action of the previous ENTER instruction CDA3100 week06-3.ppt

59 11/29/2018 ENTER Instruction CDA3100 week06-3.ppt

60 IA-32 and IA-64 Instruction Format
11/29/2018 IA-32 and IA-64 Instruction Format CDA3100 week06-3.ppt

61 Examples of Instruction Formats
11/29/2018 Examples of Instruction Formats CDA3100 week06-3.ppt

62 11/29/2018 ADD Instructions CDA3100 week06-3.ppt

63 11/29/2018 ADD Instructions CDA3100 week06-3.ppt

64 Add Instruction Description
11/29/2018 Add Instruction Description CDA3100 week06-3.ppt

65 SCAS/SCASB/SCASW/SCASD—Scan String
11/29/2018 SCAS/SCASB/SCASW/SCASD—Scan String CDA3100 week06-3.ppt

66 Next Time SSE Instructions
11/29/2018 Next Time SSE Instructions Brief Introduction to Inline Assembly Programming Using gcc CDA3100 week06-3.ppt

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