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Changes in Level 1 CSC Trigger in ORCA by Jason Mumford and Slava Valuev University of California Los Angeles June 11, 2002 http://www.physics.ucla.edu/~mumford.

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Presentation on theme: "Changes in Level 1 CSC Trigger in ORCA by Jason Mumford and Slava Valuev University of California Los Angeles June 11, 2002 http://www.physics.ucla.edu/~mumford."— Presentation transcript:

1 Changes in Level 1 CSC Trigger in ORCA by Jason Mumford and Slava Valuev University of California Los Angeles June 11, CMS Week, November Jason Mumford Slava Valuev

2 Introduction Talk given November 2001 Work since November 2001
New emulation of ALCT and CLCT Processors Bug fixes Improvements in eta and phi resolution seen Measurement of LCT rates Work since November 2001 CMS Note 2002/007 released (‘CSC Trigger Primitive Rates in ORCA’) New ALCT Processor simulation New Sector Receiver simulation Capability for stand-alone hardware test Other changes (such as data format, etc.) CMS Week, November Jason Mumford Slava Valuev

3 L1MuCSCAnodeLCTProcessor
Old vs. New - New Firmware written by Alex Madorsky, University of Florida Step 1. Pulse Extension: Old: Default = 7 bx New: Default = 6 bx Step 2. Pre-trigger Old: Start from lowest wire and look for at least 2 layers hit within a pre-trigger pattern. If any wire gives pre-trigger, proceed to pattern detection. New: There is a separate pre-trigger for every wire-group. The pre-trigger searches for hits on at least 2 layers for any pattern. Step 3. Pattern Detector Old: Only one pattern used; quality based on number of layers hit. New: There are 2 programmable ‘collision’ patterns, and 1 straight ‘accelerator’ pattern. 1 collision pattern and the accelerator pattern are accepted if each has at least 4 layers with hits. CMS Week, November Jason Mumford Slava Valuev

4 L1MuCSCAnodeLCTProcessor
Step 4: Ghost Cancellation Logic Old: Did not exist New: If a track exists adjacent to an existing track, and if the track has less quality and was detected up to 4 clocks before current track, then it is cancelled. Step 5: Track Promotion New: ‘trig_mode’ enables/disables either collision or accelerator tracks. ‘alct_mode’ gives preference to either the collision patterns or accelerator patterns. Step 6: Best Track Searcher Old: Selects 2 best tracks, but ignores a track if it is within 2 wire-groups of the previous track, has less quality, and has time within 4 bx of previous track. New: Selects 2 tracks with highest quality. CMS Week, November Jason Mumford Slava Valuev

5 L1MuCSCAnodeLCTProcessor
.orcarc Parameters: bx_width = Pulse extension width. Default = 6. 2. nph_thresh = Number of planes hit threshold for Pre-Trigger. Range = 0 to 6 CSC layers. Default = 2. 3. drift_delay = Drift delay after Pre-Trigger, 25ns steps. Range = 0 to 3 [0 to 75ns]. Default = 3. 4. nph_pattern = Pattern hits required after drift delay to allow an LCT-Trigger. Range = 0 to 6 CSC layers. Default = 4. CMS Week, November Jason Mumford Slava Valuev

6 L1MuCSCAnodeLCTProcessor
.orcarc Parameters (cont.): 5. trig_mode = Enable/Disable either Collision or Accelerator tracks. 0 = Enable both Collision and Accelerator tracks. 1 = Disable Collision tracks 2 = Disable Accelerator tracks. 3 = Kill Collision track if Accelerator track is found in the same WG. Default = 3. 6. alct_amode = ALCT Accelerator Muon Mode. 0 = Ignore Accelerator muons. 1 = Prefer Collision muons by adding Promotion bit to them 2 = Prefer Accelerator muons by adding Promotion bit to them 3 = Ignore Collision muons. Default = 1. CMS Week, November Jason Mumford Slava Valuev

7 L1MuCSCSectorReceiver
New code to simulate SR-SP design LUT’s are designed with same input/output bits as hardware logic. Old design used simplification and/or fake calculations. Example: phi calculation is now done in 2 stages (because of 2 hardware chips- phi local and phi global). Sector edge is constant for all stations New wire tilt correction Correction is applied in 4 sections instead of 3. Correction is now applied in all stations. CMS Week, November Jason Mumford Slava Valuev

8 L1MuCSCSectorReceiver
Before Sector Offset Change Entries Mean RMS UDFLW OVFLW Entries Mean E-01 RMS UDFLW OVFLW CMS Week, November Jason Mumford Slava Valuev

9 L1MuCSCSectorReceiver
After Sector Offset Change Entries Mean E-01 RMS UDFLW OVFLW Entries Mean E-01 RMS UDFLW OVFLW CMS Week, November Jason Mumford Slava Valuev

10 L1MuCSCSectorReceiver
Old Wire Tilt Correction CMS Week, November Jason Mumford Slava Valuev

11 L1MuCSCSectorReceiver
New Wire Tilt Correction CMS Week, November Jason Mumford Slava Valuev

12 L1MuCSCCorrelatedLCT Update in format of bits sent from Muon Port Card to Sector Receiver Update in format of bits sent from Sector Receiver to Sector Processor Format parallels hardware specifications CMS Week, November Jason Mumford Slava Valuev

13 L1MuCSCCorrelatedLCT Format of bits sent from MPC to SR. Trigger TDR
ORCA 6 ORCA 6.1 Valid Pattern CLCT Pattern CLCT Quality Half-/Di-Strip L/R Bend Key Strip ALCT Quality Accelerator Muon Wire Group Quality CSC Id ALCT_CLCT bx Match Anode Bxn BC0 STA STB Sync. error 1 bit /stub 8 bits/stub -- 2 bits/stub 7 bits/stub 4 bits/stub 5 bits/stub 2 bits/MPC 1 bit /MPC 3 bits/stub CMS Week, November Jason Mumford Slava Valuev

14 L1MuCSCCorrelatedLCT Format of bits sent from SR to SP. Trigger TDR
ORCA 6 ORCA 6.1 Phi Phi_b Eta (global) Accelerator muon Quality CSC Id Anode Bxn CSC ghost Error Front/Rear 12 bits/stub 5 bits/stub 6 bits/stub 1 bit /stub 3 bits/stub -- 4 bits/SR 1 bit /SR 5 bits/stub (pattern number) 1 bit /stub (not implemented) 4 bits/stub 7 bits/stub 4 bits/stub (ME1 only) 4 bits/SR (ME1 only) 1 bit /stub (ME1 only) CMS Week, November Jason Mumford Slava Valuev

15 L1MuCSCMotherboard New Definition of Quality
Old quality based on 3 bits + 1 accelerator bit New based on 4 bits 0 = Accelerator ALCT, no CLCT 1 = Accelerator ALCT, low-Pt CLCT 2 = Accelerator ALCT, high-Pt CLCT 3 = Collision ALCT, no CLCT 4 = CLCT, no ALCT 5 = Low-Pt CLCT and 8-9 layers (anode+cathode) 6 = Low-Pt CLCT and layers (anode+cathode) 7 = High-Pt CLCT pattern and 8-9 layers (anode+cathode) 8 = High-Pt CLCT pattern and 10 layers (anode+cathode) 9 = High-Pt CLCT pattern and 11 layers (anode+cathode) 10 = High-Pt CLCT pattern and 12 layers (anode+cathode) unassigned CMS Week, November Jason Mumford Slava Valuev

16 Stand-Alone Hardware Test
Written and organized by Darin Acosta, University of Florida L1MuCSCGeometryManager Manages number of CSC Chambers in each Muon Port Card L1CSC_STANDALONE Available as a pre-compiler option for hardware test CMS Week, November Jason Mumford Slava Valuev

17 Other Changes 30 degree sub-sector is now default in ME1 LCT sort
ME1/A is ignored if 30 degree sub-sector option is used. LCT sort LCTs are separated according to bx time Each bx time is sorted according to the new quality definition CMS Week, November Jason Mumford Slava Valuev

18 Outlook/Conclusion Changes in code prior to November 2001 were mostly bug fixes and upgrading code structure and management. Changes since then have been driven by hardware changes and hardware test preparation. Still things to do Finalize Sector Receiver LUT Implement Phi bend Optimize CLCT Patterns - Currently being studied by Bobby Scurlock, University of Florida Tune hardware parameters CMS Week, November Jason Mumford Slava Valuev

19 Acknowledgements We would like to thank the following for their generous time and contributions : Darin Acosta, Alex Madorsky, Bobby Scurlock (University of Florida) Bob Cousins, Jay Hauser (UCLA) Tim Cox (UC Davis) Rick Wilkinson (Caltech) Mu PRS Group CMS Week, November Jason Mumford Slava Valuev

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