1. Building a Computer I wonder where this goes? MIPS Kit ALU 1
Instruction
Memory A D 1

2. “Motivating Force” or “Inciting Incident”
THIS IS IT!
“Motivating Force” or “Inciting Incident”
This is the point in the course where the PLOT actually begins. We are now ready to build a computer.
The ingredients are all in place, now it is time to build a legitimate computer. One that executes instructions, much the way any other desktop, PDA, or other computer does.

3. Review: The MIPS ISA OP 6 5 16 26
The MIPS instruction set as seen from a Hardware Perspective
000000 rs rt rd
func
shamt
R-type: ALU with Reguster operands Reg[rd]  Reg[rs] op Reg[rt] rs rt
001XXX
immediate
I-type: ALU with constant operand
Reg[rt]  Reg[rs] op SEXT(immediate)
Instruction classes
distinguished by types:
3-operand ALU
ALU w/immediate
Loads/Stores
Branches
Jumps rs rt
10X011
immediate
I-type: Load and Store
Reg[rt]  Mem[Reg[rs] + SEXT(immediate)]
Mem[Reg[rs] + SEXT(immediate)]  Reg[rt] rs rt
10X011
immediate
I-type: Branch Instructions
if (Reg[rs] == Reg[rt]) PC  PC *SEXT(immediate)
if (Reg[rs] != Reg[rt]) PC  PC *SEXT(immediate)
00001X
26-bit constant
J-type: jump
PC  (PC & 0xf ) | 4*(immediate)

4. Design Approach Incremental Featurism +
Each instruction class can be implemented using a simple component repertoire. We’ll try implementing data paths for each class individually, and merge them (using MUXes, etc).
Steps:
1. 3-Operand ALU instructions
2. ALU w/immediate instructions
2. Load & Store Instructions
3. Jump & Branch instructions
4. Exceptions
Our Bag of Components:
Registers 1
Muxes
ALU A B
ALU & adders +
Data
Memory WD A RD
R/W
Register
File
(3-port)
RA1
RA2 WA WE
RD1
RD2
Instruction D
Memories

5. A Few ALU Tweaks
Let’s review the ALU that we built a few lectures ago. (With a few minor additions) A B
5-bit ALUFN
Sub Bool Shft Math OP
0 XX A+B
XX A-B
X X
X X
X B<<A X B>>A
X B>>>A
X A & B
X A | B
X A ^ B
X A | B
Add/Sub
Bidirectional
Barrel
Shifter
Boolean
Sub
Bool
Shft
Math …
Flags V,C N
Flag R Z
Flag

6. Instruction Fetch/Decode
Use a counter to FETCH the next instruction:
PROGRAM COUNTER (PC)
use PC as memory address
add 4 to PC, load new value at end of cycle
fetch instruction from memory
º use some instruction fields directly (register numbers, bit constant)
º use bits <31:26> and <5:0> to generate controls PC 00 A
Instruction 32
Memory + 1 30 +4 D 32 32
INSTRUCTION
WORD
FIELDS
Can be built with half-adders
OP[31:26], FUNC[5:0]
Control Logic
CONTROL SIGNALS

7. 3-Operand ALU Data Path rs rt rd WERF! 000000
100XXX
00000
R-type: ALU with Reguster operands Reg[rd]  Reg[rs] op Reg[rt] PC 00
Instruction
Memory A D +4
Rs: <25:21>
Rt: <20:16>
RA1
Register
RA2
Rd: <15:11> WA
File WD
RD1
RD2 WE
WERF 32 32
Control Logic A B
ALU
ALUFN
WERF!
ALUFN
WERF 32

8. Shift Instructions rs rt rd 000000
000XXX
shamt
R-type: ALU with Register operands sll: Reg[rd]  Reg[rt] (shift) shamt
sllv: Reg[rd]  Reg[rt] (shift) Reg[rs] PC 00
Instruction
Memory A D +4
Rt: <20:16>
Rs: <25:21>
RA1
Register
RA2
Rd: <15:11> WA
File WD
RD1
RD2 WE
WERF
shamt:<10:6>
Control Logic 1
ASEL A B
ALU
ALUFN
ASEL!
ALUFN
WERF
ASEL 32

9. ALU with Immediate rs rt 001XXX I-type: ALU with constant operand
Reg[rt]  Reg[rs] op SEXT(immediate) PC 00
Instruction
Memory A D +4
Rs: <25:21>
Rt: <20:16>
BSEL
Rd:<15:11>
Rt:<20:16> 1
RA1
Register
RA2 WA WA
File WD
RD1
RD2 WE
WERF
ASEL 1
shamt:<10:6>
imm: <15:0>
SEXT
SEXT 1
BSEL
Control Logic
SEXT A B
ALU
BSEL!
BSEL
ALUFN
SEXT …
ALUFN
...
WERF
ASEL
… …

10. Load Instruction rs rt 100011 I-type: Load
immediate
I-type: Load
Reg[rt]  Mem[Reg[rs] + SEXT(immediate)] PC 00
Instruction
Memory A D +4
Rs: <25:21>
Rt: <20:16>
BSEL
Rd:<15:11>
Rt:<20:16> 1
RA1
Register
RA2 WA WA
File WD
RD1
RD2 WE
WERF
ASEL 1
shamt:<10:6>
Imm: <15:0>
SEXT
SEXT
Control Logic 1
BSEL
SEXT A B
BSEL
ALU WD
R/W Wr
ALUFN
WDSEL
ALUFN
Data Memory Wr 32
Adr RD
WERF
ASEL 32
WDSEL

11. Store Instruction rs rt 10X011 I-type: Store
immediate
I-type: Store
Mem[Reg[rs] + SEXT(immediate)]  Reg[rt] PC 00
Instruction
Memory A D +4
Rs: <25:21>
Rt: <20:16>
BSEL
Rd:<15:11>
Rt:<20:16> 1
RA1
Register
RA2 WA WA
File WD
RD1
RD2 WE
WERF
ASEL 1
SEXT
BSEL
shamt:<10:6>
Imm: <15:0>
Control Logic 32
No WERF!
SEXT A B
BSEL
ALU
Data Memory RD WD
R/W
Adr Wr
ALUFN
WDSEL
ALUFN Wr
WERF
ASEL
WDSEL

12. PC<31:29>:J<25:0>:00
JMP Instructions
PC<31:29>:J<25:0>:00
00001X
26-bit constant
J-type:
j: PC  (PC & 0xf ) | 4*(immediate)
jal: PC  (PC & 0xf ) | 4*(immediate);
Reg[31]  PC + 4
PCSEL 6 5 4 3 2 1 PC 00
Instruction
Memory A D +4
Rs: <25:21>
Rt: <20:16>
WASEL
J:<25:0>
Rd:<15:11> 1 2 3
Rt:<20:16>
RA1
Register
RA2
“31” WA WA
File WD
“27”
RD1
RD2 WE
WERF
ASEL 1
SEXT
BSEL
shamt:<10:6>
Imm: <15:0>
Control Logic
PCSEL
WASEL
SEXT A B
BSEL
ALU
Data Memory RD WD
R/W
Adr Wr
ALUFN
WDSEL
ALUFN Wr
WERF
ASEL
PC+4 32
WDSEL

13. PC<31:29>:J<25:0>:00
BEQ/BNE Instructions
PC<31:29>:J<25:0>:00 rs rt BT
10X011
immediate
PCSEL 1 2 3 4 5 6
R-type: Branch Instructions
if (Reg[rs] == Reg[rt]) PC  PC *SEXT(immediate)
if (Reg[rs] != Reg[rt]) PC  PC *SEXT(immediate) PC 00
Instruction
Memory A D
That “x4” unit is trivial. I’ll just wire the input shifted over 2–bit positions. +4
Rs: <25:21>
Rt: <20:16>
WASEL
Rd:<15:11>
Rt:<20:16> 1 2 3
“31”
“27”
J:<25:0>
RA1
Register
RA2 WA WA
File WD
RD1
RD2 WE
WERF
ASEL 1
SEXT
BSEL
shamt:<10:6>
Imm: <15:0> Z x4
Why add, another adder? Couldn’t we reuse the one in the ALU? Nope, it needs to do a subtraction.
Control Logic +
PCSEL
WASEL BT
SEXT A B
BSEL
ALU
Data Memory RD WD
R/W
Adr Wr
ALUFN
WDSEL
ALUFN Wr Z
WERF
ASEL
PC+4 32
WDSEL

14. Jump Indirect Instructions
PC<31:29>:J<25:0>:00
000000 rs rt rd
00100X
00000 JT BT
PCSEL 1 2 3 4 5 6
R-type: Jump Indirect, Jump and Link Indirect
jr: PC  Reg[rs]
jalr: PC  Reg[rs], Reg[rd]  PC + 4 PC 00
Instruction
Memory A D +4
Rs: <25:21>
Rt: <20:16>
WASEL
Rd:<15:11>
Rt:<20:16> 1 2 3
“31”
“27”
J:<25:0>
RA1
Register
RA2 WA WA
File WD
RD1
RD2 WE
WERF
ASEL 1
SEXT
BSEL
shamt:<10:6>
Imm: <15:0> JT Z x4
Control Logic +
PCSEL
WASEL BT
SEXT A B
BSEL
ALU
Data Memory RD WD
R/W
Adr Wr
ALUFN
WDSEL
ALUFN Wr Z
WERF
ASEL
PC+4 32
WDSEL

15. PC<31:29>:J<25:0>:00
Loose Ends
PC<31:29>:J<25:0>:00 rs rt JT BT
001XXX
immediate
PCSEL 1 2 3 4 5 6
I-type: set on less than & set on less than unsigned immediate
slti: if (Reg[rs] < SEXT(imm)) Reg[rt]  1; else Reg[rt]  0
sltiu: if (Reg[rs] < SEXT(imm)) Reg[rt]  1; else Reg[rt]  0 PC 00
Instruction
Memory A D +4
Rs: <25:21>
Rt: <20:16>
Reminder:
To evaluate (A < B) we
first compute
A-B and look at the flags.
LT = N  V
LTU = C
WASEL
Rd:<15:11>
Rt:<20:16> 1 2 3
“31”
“27”
J:<25:0>
RA1
Register
RA2 WA WA
File WD
RD1
RD2 WE
WERF
ASEL 1
SEXT
BSEL
shamt:<10:6>
Imm: <15:0> Z N JT V C x4
Control Logic +
PCSEL
WASEL BT
SEXT A B
BSEL
ALU
Data Memory RD WD
R/W
Adr Wr
ALUFN
WDSEL
ALUFN Wr N V C Z
WERF
ASEL
PC+4 32
WDSEL

16. PC<31:29>:J<25:0>:00
More Loose Ends
PC<31:29>:J<25:0>:00
000000 rs rt rd
10101X
00000 JT BT
PCSEL 1 2 3 4 5 6
R-type: set on less than & set on less than unsigned
slt: if (Reg[rs] < Reg[rt]) Reg[rd]  1; else Reg[rd]  0
sltu: if (Reg[rs] < Reg[rt]) Reg[rd]  1; else Reg[rd]  0 PC 00
Instruction
Memory A D +4
Rs: <25:21>
Rt: <20:16>
WASEL
Rd:<15:11>
Rt:<20:16> 1 2 3
“31”
“27”
J:<25:0>
RA1
Register
RA2 WA WA
File WD
RD1
RD2 WE
WERF
ASEL 1
SEXT
BSEL
shamt:<10:6>
Imm: <15:0> N JT Z V C x4
Control Logic +
PCSEL
WASEL BT
SEXT A B
BSEL
ALU
Data Memory RD WD
R/W
Adr Wr
ALUFN
WDSEL
ALUFN Wr N V C Z
WERF
ASEL
PC+4 32
WDSEL

17. PC<31:29>:J<25:0>:00
LUI Ends
PC<31:29>:J<25:0>:00 rt JT BT
001XXX
00000
immediate
PCSEL 1 2 3 4 5 6
I-type: Load upper immediate
lui: Reg[rt]  Immediate << 16 PC 00
Instruction
Memory A D +4
Rs: <25:21>
Rt: <20:16>
WASEL
Rd:<15:11>
Rt:<20:16> 1 2 3
“31”
“27”
J:<25:0>
RA1
Register
RA2 WA WA
File WD
RD1
RD2 WE
WERF
Imm: <15:0>
SEXT JT
SEXT Z N V C x4
shamt:<10:6>
Control Logic +
“16” 1 2
ASEL 1
BSEL
PCSEL
WASEL BT
SEXT A B
BSEL
ALU
Data Memory RD WD
R/W
Adr Wr
ALUFN
WDSEL
ALUFN Wr N V C Z
WERF
ASEL
PC+4 32
WDSEL

18. Reset, Interrupts, and Exceptions
FIRST, we need some way to get our machine into a known initial state. This doesn’t mean that all registers will be initialized, just that we’ll know where to fetch the first instruction. We’ll call this control input, RESET
We’d also like RECOVERABLE INTERRUPTS for
• FAULTS (eg, Illegal Instruction) CPU or SYSTEM generated [synchronous]
• TRAPS & system calls (eg, read-a-character) CPU generated [synchronous]
• I/O events (eg, key struck) externally generated [asynchronous]
EXCEPTION GOAL: Interrupt running program, invoke exception handler, return to continue execution.
These are “Software” notions of synchrony and asynchrony.
(Implemented as an “agreed upon” Illegal instruction)

19. PC<31:29>:J<25:0>:00
Exceptions 0x 0x
PC<31:29>:J<25:0>:00 0x JT BT
Reset: PC  0x
PCSEL 1 2 3 4 5 6
Bad Opcode: Reg[27]  PC+4; PC  0x
IRQ: Reg[27]  PC+4; PC  0x PC 00
Instruction
Memory A D +4
Rs: <25:21>
Rt: <20:16>
WASEL
Rd:<15:11>
Rt:<20:16> 1 2 3
“31”
“27”
J:<25:0>
RA1
Register
RA2 WA WA
File WD
RD1
RD2 WE
WERF
Imm: <15:0>
RESET
SEXT N JT
SEXT
IRQ Z V C x4
ASEL 2
shamt:<10:6>
“16” 1
Control Logic + 1
BSEL
PCSEL
WASEL BT
SEXT A B
BSEL
ALU
Data Memory RD WD
R/W
Adr Wr
ALUFN
WDSEL
ALUFN Wr N V C Z
WERF
ASEL
LSEL
PC+4 32
WDSEL

20. MIPS: Our Final VersionWA PC +4
Instruction
Memory A D
Register
File
RA1
RA2
RD1
RD2
ALU B WD WE
ALUFN
Control Logic
Data Memory RD
R/W
Adr Wr
WDSEL
BSEL
J:<25:0>
PCSEL
WERF 00
PC+4
Rt: <20:16>
Imm: <15:0>
ASEL
SEXT + x4 BT Z
WASEL
Rd:<15:11>
Rt:<20:16> 1 2 3
PC<31:29>:J<25:0>:00 JT N V C
Rs: <25:21>
shamt:<10:6> 4 5 6
“16”
IRQ 0x 0x 0x
RESET
“31”
“27”
This is a complete 32-bit processor.
Although designed in one class lecture, it executes the majority of the MIPS R2000 instruction set.
Executes one instruction per clock
All that’s left is the control logic design

21. MIPS Control The control unit can be built as a large ROM X 1 4 00 6 3
Instruction R E S T I Q Z N V C P L
S E X T
WA S E L
W D S E L
ALUFN
Sub Bool Shft Math
W R
W E R F A
BSEL X 1 4 00 6 3
add
sll
andi lw sw
beq