1. Introduction toVLSI Programming Lecture 4: Data handshake circuits
(course 2IN30)
Prof. dr. ir.Kees van Berkel
Dr. Johan Lukkien

2. Time table 2005 date class | lab subject Aug. 30 2 | 0 hours
intro; VLSI
Sep. 6
3 | 0 hours
handshake circuits
Sep. 13
handshake circuits assignment
Sep. 20
Tangram
Sep. 27
no lecture
Oct. 4
Oct. 11
1 | 2 hours
demo, fifos, registers | deadline assignment
Oct. 18
design cases;
Oct. 25
DLX introduction
Nov. 1
low-cost DLX
Nov. 8
high-speed DLX
Nov. 29
deadline final report
11/30/2018
Kees van Berkel

3. Lecture 4 Outline: Recapitulation Lecture 3
Data encoding; push and pull handshakes
Tangram assignment command
Handshake components: handshake latch, transferrer, multiplexer, adder
Handshake circuits & Tangram programs: fifo buffers and shift registers
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Kees van Berkel

4. Header: handshake circuit
L=0 L=1
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Kees van Berkel

5. Sequencer realizationx ar bk br cr ck ak
Sequencer: area, delay, energy:
Area: 5 gate equivalents
Delay per cycle: 8 gate delays
Energy per cycle: 10 transitions
11/30/2018
Kees van Berkel

6. Handshake signaling and data
request ar
active side
passive side
acknowledge ak
data ad
push channel
versus
pull channel
request ar
active side
passive side
acknowledge ak
data ad
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Kees van Berkel

7. Handshake signaling: push channel
time
req ar
ack ak
early ad
broad ad
late ad
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Kees van Berkel

8. Data bundling
In order to maintain event ordering at both sides of a channel, the circuit must satisfy data bundling constraint:
for push channel: delay along request wire must exceed delay of data wire;
for pull channel: delay along acknowledge wire must exceed delay of data wire.
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Kees van Berkel

9. Handshake signaling: pull channel
When data wires are invalid: multiple and incomplete transitions allowed.
req ar
time
ack ak
early ad
broad ad
late ad
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Kees van Berkel

10. Tangram assignment x:= f(y,z)yw zw y f z  
xw0 | x xr
xw1 y f z   y f z   | x | x
Handshake circuit
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Kees van Berkel

11. Four-phase data transfer
time
r / br
ba / cr   b c
ca / a
bd / cd
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Kees van Berkel

12. Handshake latch
[ [ w ; [w : rd:= wd] [] r ; r ] ]
1-bit handshake latch: wd  wr  rd  wd  wr  rd  wk = wr rk = rr x r w wd wr rd
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Kees van Berkel

13. N-bit handshake latch ... wr wd1 rd1 wd2 wk rd2 wdN rdN rr rk
area, delay, energy
area: 2(N+1) gate eqs.
delay per cycle: gate delays
energy per write cycle: *2N transitions, in average
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Kees van Berkel

14. Transferrer ar ak a br ck bk cr  bd cd
[ [ a : (b ; c)] ; [ a : (b ; cd:= bd ; c ; cd:= )] ]
ar ak br bk bd ck cr cd  a b c
11/30/2018
Kees van Berkel

15. Multiplexer | Restriction: ar  br must hold at all times! a c b
[ [ a : c ; a : (cd:= ad; c ; cd:= ) [] b : c ; b : (cd:= bd; c ; cd:= ) ] ]
Restriction: ar  br must hold at all times! | a b c
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Kees van Berkel

16. Multiplexer realization
control circuit
data circuit
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Kees van Berkel

17. Logic/arithmetic operator
[ [ a : (b || c) ] ; [ a : ((b || c) ; ad:= f(bd , cd ))] ]
Cheaper realization (delay sensitive):
[ [ a : (b || c) ] ; [ a : ((b || c) ; ad:= f(bd , cd ))] ; “delay” ; ad:=  ] f b c a
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Kees van Berkel

18. A one-place fifo buffer
byte = type [0..255]
& BUF1 = main proc (a?chan byte & b!chan byte). begin x: var byte | forever do a?x ; b!x od end
BUF1 a b
11/30/2018
Kees van Berkel

19. A one-place fifo buffer
byte = type [0..255]
& BUF1 = main proc (a?chan byte & b!chan byte). begin x: var byte | forever do a?x ; b!x od end   ;  x b a   ; ;   a a  x x x x  b b
11/30/2018
Kees van Berkel

20. 2-place buffer BUF1 a b c byte = type [0..255]
& BUF1 = proc (a?chan byte & b!chan byte). begin x: var byte | forever do a?x ; b!x od end
& BUF2: main proc (a?chan byte & c!chan byte). begin b: chan byte | BUF1(a,b) || BUF1(b,c) end
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Kees van Berkel

21. Two-place ripple buffer
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Kees van Berkel

22. Two-place wagging buffer
byte = type [0..255] & wag2: main proc (a?chan byte & b!chan byte). begin x,y: var byte | a?x ; forever do (a?y || b!x) ; (a?x || b!y) od end
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Kees van Berkel

23. Two-place ripple register
… begin x0, x1: var byte | forever do b!x1 ; x1:=x0; a?x0 od end
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Kees van Berkel

24. 4-place ripple register
byte = type [0..255] & rip4: main proc (a?chan byte & b!chan byte). begin x0, x1, x2, x3: var byte | forever do b!x3 ; x3:=x2 ; x2:=x1 ; x1:=x0 ; a?x0 od end
11/30/2018
Kees van Berkel

25. 4-place ripple registerx0 x1 x2 x3 x0 x0 x0 x1 x1 x2 x2 x3 x3 x3
area : N (Avar + Aseq )
cycle time : Tc = (N+1) T:=
cycle energy: Ec = N E:=
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Kees van Berkel

26. Introducing vacancies
… begin x0, x1, x2, x3, v: var byte | forever do (b!x3 ; x3:=x2 ; x2:=v) || (v:=x1 ; x1:=x0 ; a?x0) od end
what is wrong?
11/30/2018
Kees van Berkel

27. Introducing vacancies
forever do ((b!x3 ; x3:=x2) || (v:=x1 ; x1:=x0 ; a?x0)) ; x2:=v od
or:
forever do ((b!x3 ; x3:=x2) || (v:=x1 ; x1:=x0)) ; (x2:=v || a?x0) od
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Kees van Berkel

28. “synchronous” 4-p ripple registerm0 s0 m1 s1 m2 s2 m3 x0 b m0 s0 m1 s1 m2 s2 m3 x0 b m0 s0 m1 s1 m2 s2 m3 x0 b m0 s0 m1 s1 m2 s2 m3 x0 b m0 s0 m1 s1 m2 s2 m3 x0 b
forever do (s0:=m0 || s1:=m1 || s2:=m2 || b!m3 ) ; ( a?m0 || m1:=s0 || m2:=s1 || m3:=s2) od
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Kees van Berkel

29. 4-place wagging registerx0 x1 x2 x3 y0 y1 a b a x0 x0 x1 x1 x2 b a b a a y0 y1 b b y0 y1
forever do b!x1 ; x1:=x0 ; a?x0 ; b!y1 ; y1:=y0 ; a?y0 od
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Kees van Berkel

30. 8-place register 4-way wagging
forever do b!u1 ; u1:=u0 ; a?u0 ; b!v1 ; v1:=v0 ; a?v0 ; b!x1 ; x1:=x0 ; a?x0 ; b!y1 ; y1:=y0 ; a?y0 od
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Kees van Berkel

31. Four 88 shift registers compared
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Kees van Berkel

32. Next session: lecture 5 Outline: Tangram overview
Compilation: Tangram  Handshake Circuits
Tools
Demonstration
Lab work: assignment “fifos and registers”
11/30/2018
Kees van Berkel