Automatic Test Pattern Generation

Automatic Test Pattern Generation
Sungho Kang Yonsei University

Outline Introduction Applications Boolean Difference D Algorithm PODEM
FAN Heuristics Test Compaction Sequential ATPG

Test Pattern Generation
Introduction Test generation Manual generation Pseudo random generation Algorithmic (or deterministic) test generation Automatic Test Pattern Generation (ATPG) Calculate the set of test patterns from a description of the logic network and a set of assumptions called fault models

ATPG Result of ATPG Cost of ATPG Quality of the generated tests
Introduction Result of ATPG Find a test pattern Redundant fault Run out of time/memory (Aborted fault) Cost of ATPG Low CPU time Quality of the generated tests High fault coverage Cost of Applying Test Small number of tests Fault Coverage # of detected faults / # of faults # of detected faults / (# of faults - # of redundant faults) (# of detected faults + # of redundant faults) / # of faults

Definition Fault Excitation Fault Propagation
Introduction Fault Excitation The process of finding a sufficient set of PI values to cause the fault site in the good circuit to have a value opposite to the faulty value Fault Propagation The process of moving the effect of a fault closer to a PO

Definition Single Fault Assumption Implication
Introduction Single Fault Assumption The assumption that one and only one fault is present in a given circuit at a time Implication The process of determining the unique values implied by already assigned values The process can cause both forward and backward assignment of values

Definition Reconvergent fanout Line Justification
Introduction Reconvergent fanout A fanout node, two or more of whose branches eventually are used as inputs to the same element The element at which the branch reconverge is called the point of reconvergence Line Justification The process of finding a set of PI values which cause the line to achieve the desired value Essentially the same as backdrive with conflict resolution

Definition Backtracking
Introduction Backtracking Retracing in the search space to resolve the conflict by trying alternate assignments at previously assigned nodes Should store previously determined values

Definition A test cannot detect both s-a-0 and s-a-1
Introduction A test cannot detect both s-a-0 and s-a-1 Reconvergent fanout free circuits are easy to generate tests Redundant fault

General Outline of ATPG
Introduction Choose a fault if imply-and-check() = FAILURE return FAILURE if fault effect at PO and all lines are justified return SUCCESS if no fault effect can be propagated to a PO select an unsolved problem repeat select one untried way to solve it if solve( ) = success until all ways to solve it have been tried

ATPG Example Introduction F output s-a-0

ATPG Example Introduction G output s-a-1

ATPG Example Introduction H s-a-1

Fault Independent ATPG
Introduction Goal is to derive a set of tests that detect a large set of faults without targeting individual faults Random Pseudo random Vectors are generated by a deterministic algorithm such that statistical properties are similar to those of a randomly selected set Use LFSR Use Software Assumptions Input vectors are uniformly distributed Input vectors are independently generated But most of pseudo random vector generator work such that an already generated vector is not repeated

2 Phase ATPG Random + Deterministic while an exit condition happens
Introduction Random + Deterministic while an exit condition happens get a vector fault simulate the vector if the vector detects faults add the vector to the test set discard the faults for all remaining faults select a fault generate a vector if successful add the vector in the test set

Boolean Difference Boolean Difference

Boolean Difference : Chain Rule

Boolean Difference Test Pattern Generation
Test for a s-a-0 is xyz = (1 1 0) Set x = 1 to provoke fault Set y = 1, z=0 to sensitize fault site to PO

Boolean Difference To Propagate Fault, set x=1, and y or z=0
c = v’ + w’ For c s-a-1,must set c=0 so v = w = 1 Test for c s-a-1

Boolean Difference : Example
Test for fault G2 s-a-0

D Algorithm Path Sensitization + Signal Propagation Path Sensitization
To generate a test to detect a fault Specify inputs so as to generate the appropriate value at the site of the fault 0 for s-a-1 and 1 for s-a-0 Select a path from the site of the fault to an output and specify additional signal values to propagate the fault signal along this path to the output Specify inputs values so as to produce the signal values specified in the previous step For fault propagation, Gate Type Other inputs AND NAND All must 1 OR NOT All must 0

D Algorithm ATPG is a search problem:
Determine signal value assignments to internal lines as well as primary inputs which solve the fault activation and propagation tasks. Two kinds of Signal value assignments: 1) assigned by decision, Which can be wrong, 2) uniquely implied by other values Implicit enumeration of the complete search space: Backtracking or branch and bound using decision tree

D Algorithm : Example G s-a-1 To generate 0 at the output of G A=B=C=1
To propagate through J output of F=1 It implies A=B=0 Contradicts!!!

D Algorithm D Algorithm Introduce D and D’

D Algorithm Algorithm D frontier D drive 1) Initialize all nodes to X
2) Select a fault  3) Select a pdcf of  4) Implication (forward and backward) 5) D drive 6) If not reached PO, go to 4) 7) Line justification D frontier Set of elements whose output values are unspecified but whose input has some signal D or D’ D drive Attempts to propagate D or D’ to the output of elements

Primitive Cube D Algorithm For an element E which realizes the combinational function f, the primitive cubes(pc) of f are a typical representation of the prime implicants of f and f’ Example Prime implicants of f Prime implicants of f ’

Primitive D Cube D Algorithm A primitive D-cube of a fault (pdcf) specifies the minimal input conditions which must be applied to E in order to produce an D or D’ at the output of E An input condition produces a faulty output D(D’) if it is contained in a prime implicant of f(f’) and also contained in a prime implicant of f’(f )

Primitive D Cube Example Prime implicants of f 
D Algorithm Example Primitive D-cube a fault(pdcf) Prime implicants of f  Prime implicants of f ’  where

Propagation D Cube D Algorithm The propagation D-cubes of an element specify minimal input conditions to the element which are required to propagate an D or D’ on an input (or inputs) to the output of the element Can be derived by intersecting 0 and 1 with different values on an input Example

Propagation D Cube Consider 3 input NAND
D Algorithm Consider 3 input NAND Primitive cubes and Primitive D-cubes of faults Propagation D-cubes

D Algorithm Generate a test for f s-a-0
Initial problem: Justify(f, 1), Propagate(f, D) (1) Justify(f, 1) solved by a=b=1 (2) Propagate(f, D) solved by solving Justify(g, 0) and Propagate(h, D) (3) Justify(g,0) solved by setting g to 0, which is, c to 0 (4) Propagate(h, D) leads to Justify(i, 1), which is ,e=0 Question: what is the decision made here?

D Algorithm Consider the fault G1 s-a-1 To activate: Justify(G1,0)
To propagate: either via G5 or G6 Take G5, i.e., Justify(G2,1), which can not be solved together with Justify(G1,0) => Contradiction, Backtracking Take G6, Justify(G4,1), which is solved by Justify(G3,0) and e=0, and eventually c=1

D Algorithm Wrong Decision Consider g s-a-1 fault
To activate h=0 Unique path to PO, through p and s (1) Need to have e=f=1, q=r=1 (2) In order to have q=1, either l=1 or k=1 (3) Decided to set l=1, which leads to c=d=1, which in turn leads to r=0, which is a contradiction (4) Backtrack and set k=1, implying a=b=1

D Algorithm Implication Decision tree
A process of determining uniquely determined value implied by other(decided) values Decision tree node: problem to solve branch: one available way to solve the problem

D Algorithm Implicit Enumeration
Combinational ATPG ALG is exhaustive, i.e., it is guaranteed to find a solution if one exists. Hence, if the ALG fails to find a solution, no solution exists. Although the ALG exhausts the search space, it only does it implicitly

D Algorithm Complexity issues
Worst case complexity of all ATPG ALG is exponential, Which is characterized by many remade decisions; Search is abandoned when the number of backtracks or CPU time reaches a specified limit. To minimize the number of backtracks perform as many implications as possible, i.e., maximum implication principle

D Algorithm D-Frontier J-Frontier
A collection of all gates whose output is currently x, but one of more of its inputs are D or D. Error propagation consists of selecting one gate from D-frontier and assigning values to the unspecified gate inputs so that the output becomes D or D J-Frontier A collection of all gates whose output value is set to 1 or 0, but is not implied by its input values

D Algorithm Implication Process
A modified zero-delay simulation procedure which needs to propagate values backwards as well as forwards. (1) Compute all values that can be uniquely determined. (2) Check for consistency and assign values (3) Maintain the D-frontier and the J-frontier About 50% of ATPG time is spent on implication, hence good implementation is warranted.

D Algorithm D Algorithm Forward implication(binary values)

D Algorithm D Algorithm Forward Implication(Error)

D Algorithm D Algorithm Backward implication

D Algorithm D Algorithm Unique D-Frontier Unique Path Sensitization

D Algorithm X-path Check
X-path Check is merged into the Unique Sensitization in the modern ATPG ALG(See SOCRATES)

X Path Check X path check
D Algorithm X path check Let s be a signal on the fault sensitization path If s has 0 or 1, the fault cannot be propagated Check the value using forward implication

D Algorithm D Algorithm Reversing incorrect decisions

D Algorithm D Algorithm D-alg() { if(!imply()) return FAILURE;
if(error not a PO) { if(!D-Frontier) return(FAILURE); repeat { select an untried gate (G) from the D-frontier; c = controlling value of G assign c to every input of G with value x if(D-alg()) then return(SUCCESS); } until all gates from D-frontier have been tired return FAILURE; } /* error propagated to a PO */ if(!J-Frontier) return(SUCCESS); select a gate (G) from the J-Frontier c = controlling value of G repeat { select an input (j) of G with value x assign c to j if(D-alg()) return(success); } until all inputs of G are specified /* no more choice */ return(FAILURE); }

D Algorithm D Algorithm Multiple Path Sensitization

D Algorithm D Algorithm Multiple Path Sensitization is required

D Algorithm Example D Algorithm G1 s-a-0

D Algorithm : Example D Algorithm G1 s-a-0

9V Algorithm Problem of D Algorithm
Selection of fanout branch - increasing exponentially Advantage is mainly due to the higher degree of freedom At fanout point having a fanout of N, at most N attempts have to be made out D requires 2N-1

9V Algorithm Avoid the need of considering all subsets of D-Frontier.
5 value system: 1, 0, D, D’, X 9 value system: 1/1, 0/0, 1/0, 0/1, 1/x, 0/x, x/1, x/0, x/x Logic operation between two composite values can be carried out separately, and then composing the results. In actual implementation, table driven evaluation is employ 9 Value system is necessary when multiple fault effects need to be considered as in sequential ATPG

9V Algorithm 9V Algorithm AND

9V Algorithm 9V Algorithm Execution trace of 9-V ALG

9V Algorithm : Example 9V Algorithm G1 s-a-0

PODEM Path Oriented DEcision Making Search space on PIs
Implicit space enumeration Algorithm PODEM() if (Error at PO) return SUCCESS if (test not possible) return FAILURE get an objective backtrace the objective to PI imply the PI value if PODEM() == SUCCESS imply PI with X value assume target fault is I s-a-v objective() if ( the value of I is X ) return (I, v’) select a gate(G) from the D frontier select an input j of G with value X c = controlling value of G return ( j, c’)

PODEM PODEM PODEM employs Direct search of input space, i.e., the decisions such as selection of a gate from the D-Frontier or a way of justifying the value of a gate from the J-Frontier are mapped into PI values. Backtrace Backtrace(k,vk) { v = vk; while(k is a gate output) { i = inversion of k select an input (j) of k with value x v =v + i k = j } /* k is a PI */ return(k,v)

PODEM PODEM Objective Either activate the fault at fault site when it is not activate, or push the D-Frontier forward once the fault is activated Objective() { /* the target fault is l s-a-v */ if(the value of l is x) return(l,v) select a gate (G) from the D-Frontier select an input (j) of G with value x c = controlling value of G return (j, c) }

PODEM Recursive Version of PODEM Algorithm Podem() {
if(error at PO) return(SUCCESS); if(test not possible) return(FAILURE); (k, vk) = Objective(); (j, vj) = Backtrace(k, vk); imply(j, vj); if(PODEM()) return(SUCCESS); imply(j, x); return(FAILURE); }

PODEM PODEM PODEM search process is based on direct implicit enumeration of the possible input vectors PODEM does not need consistency check, as conflicts can never occur; the J-Frontier, since there are no values that require justification, backward implication, because values are propagated only forwards. In PODEM backtracking is implicitly done by simulation rather than by an explicit save/restore process

PODEM PODEM PODEM execution trace

PODEM Example PODEM a s-a-1 : using D

PODEM Example PODEM a s-a-0 : using PODEM

PODEM Example PODEM Continued Decision Tree

Decision Tree PODEM Example circuit

Decision Tree(Continued)
PODEM Example circuit

PODEM Very effective for ECAT
Made up some number of XOR trees with reconvergence of the generated parity signals Choose the easiest one when 0 on AND output Choose the hardest one when 1 on AND output

PODEM Example PODEM K s-a-0

PODEM Example PODEM M s-a-0

FAN FANout Oriented ATPG
Stop the backtrace at a headline and postpone the line justification for the headline to the last Multiple backtrace Free line Gate output whose predecessors are fanout free Head line Free line that enters a region of reconvergent fanout

FAN The Concept of Headlines
A line that is reachable from at least one stem is said to be bound. A line that is not bound is said to be free. A headline is a free line that direct feeds a bound line.

FAN Assume that we want to set J=0
Assume that with PI assignments previously made, setting J=0 causes D frontier empty Failure

FAN Multiple backtrace is concurrent tracing of more than one path.

FAN Objective of Multiple Backtrace (s, n0(s), n1(s))
where s is an objective line, n0(s) is the number of times the objective logic level 0 is required at s, and n1(s) is the number of times the objective logic level 1 is required at s. Multiple backtrace is given a set of initial objectives, and a set of current objectives are maintained during the backtrace process, and a set of head objectives and fanout objectives are computed.

FAN Initial Objectives
(s, 1, 0) for line s set to 0, (s, 0, 1) for line s set to 1 Determining next objectives for Basic gates

FAN FAN Multiple backtrace at Fan-out points

FAN FAN Computation of n0 and n1

FAN Multiple Backtrace a set of objectives and determines
Multiple backtrace starts with a set of objectives and determines an assignment k=vk that is likely to achieve some original objectives or to show that some objectives can not be achieved together.

Multiple Backtrace FAN Determines an assignment that is likely either to contribute achieving a subset of the original objectives or to show that some subset of the original objectives cannot be simultaneously achieved Different objectives are backtracked to its same stem with conflicting at its branches Multiple backtrace stops backtracing when a stem is reached and keeps track of the number of times a 0 and 1 have been requested on the stem

Multiple Backtrace Algorithm
FAN Mbacktrace(current_objectives) repeat remove one entry(k, vk) from current_objectives if k is head line add (k, vk) to head_objectives else if k is a fanout branch j=stem of k increment number of requests at j for vk add j to stem_objectives else i=inversion of k c=controlling value of k if (vk  i =c) select an input j of k with value X add(j, c) to current_objectives for every input j of k with value X add (j, c’) to current_objectives until current_objectives id NULL if stem_objectives is not NULL remove the highest level stem k from stem_objectives vk=most requested value of k if k has contradictory requirements and not reachable from target fault return(k, vk) add (k, vk) to current_objectives return Mbacktrace(current_objectives) remove one objective(k, vk) from head_objectives

Multiple Backtrace FAN Example

FAN Algorithm FAN() if imply_and_check()=FAILURE return FAILURE
if fault effect at PO and all bound lines are justified justify all unjustified head lines return SUCCESS if fault effect at PO and D frontier=NULL add every unjustified bound line to current_objectives select one gate G from the D frontier c=controlling value of G for every input j of G with value x add(j,c’) to current_objectives (i, vi)=Mbacktrace(current_objectives) assign(i,vi) if FAN()=SUCCESS assign(i,vi’) rerturn FAILURE

FAN Fan-out point Objective Otherwise, backtrace would be continued.
After the set of current objectives become empty, a fan-out point objective is taken out, if one exists. Two conditions for stopping backtrace a) The objective is not reachable from the fault line, and b) Both n0(p) and n1(p) are nonzero => logic value 0(1) is assigned if n0(p)  () n1(p) to the fan-out point, i.e., the fan-out point objective becomes the final objective. Otherwise, backtrace would be continued.

FAN Determination of final objectives Backtrace Flag
When backtrace stops at C, each head line is taken out one by one from the set of head objectives, and the associated value is assigned to be implied. Backtrace Flag Backtrace Flag determines Whether multiple backtrace starts from the set of initial objectives or continues from the last multiple backtrace terminated at a fan-out point. The backtrace does not continue a) if the last objective was to propagate D or D and D-frontier has changed or b) if objective was to justify unjustified and all unjustified lines have been justified.

FAN FAN

FAN Unique Path Sensitization
FAN extends the X-Path check of PODEM to use the structural dominance concept. Every path from a singleton D-Frontier gate always goes through a gate and an off-path input of the gate is free from fault effect, the non controlling value must be applied.

FAN FAN Unlike PODEM, FAN assigns logic values to internal lines other than head lines since fanout points can be final objectives and unique sensitization assigns logic values to unjustified internal lines. Hence, backward implication as well as forward implication is required as in D-ALG

FAN FAN Backtracking The decision tree of FAN is identical to PODEM, that is, an ordered list of nodes, with each identifying current assignment of either 0 or 1, and a flag indicating whether the current assignment is an alternative. On the contrary to PODEM, backtracking in FAN needs some saving and restoring of status.

FAN FAN

FAN Example FAN M-L s-a-0 using PODEM

FAN Example FAN M-L s-a-1 using FAN

SOCRATES Goals Goals achieved by
SOCRATES is a direct descendant of FAN with improved implication procedure, improved unique sensitization procedure, and improved multiple backtracing procedure. Goals (1) minimizing the unidentified non-solution area, and (2) avoiding all non-solution areas during the search process Goals achieved by (1) optimize the pruning of the search space (2) reduce the number of backtrackings (3) recognize conflicts as early as possible (4) avoid useless backtracking in unidentified nonsolution areas

Dominator SOCRATES A signal y is said to dominate a signal x if all directed paths from x to the POs pass through y Dominator The set of signal that dominate signal x The fault effect should pass through dominators Off-path inputs of dominators are assigned noncontrolling values to propagate fault effect Example Dominators of signal C : G2 and G5 Thus D=0 and J=1

SOCRATES Improved Implication Procedure
Implications from a = 1 Implications from f = 0 An Improved Implication Procedure Logic contrapositive (P=>Q) <=> (~Q=>~P)

Static learning SOCRATES To assign a logic value to a certain signal of the circuit, perform This is done for all signals of the circuit for both logic value 0 and 1 Example B=1 => F=1 F=0 => B=0

Static Learning Algorithm learn() for every signal I
SOCRATES Algorithm learn() for every signal I assign value(i, 0) implication() analyze_result(i) assign value(i, 1) analye_result(i) analyze_result(i) vi=value of I for every signal j with value of jx and with j  I vj=value of j g=gate with output signal j tg=gate type of g if [(vj=1 and (tg=AND or tg=NOR)) or (vj=0 and (tg=NAND or tg=OR)) or tg=XOR or tg=XNOR] if there is no direct path from I to j save_implication(j=vj’ >> i=vi’)

Static Learning Criterion
SOCRATES Let i be the signal at which the current learning step has been initialized by the assignment i = v(i) and let j be a signal to which the fixed logic value v(j) (0 or 1) has been assigned during the implication procedure ( i = v(i) ) => (j = v(j) ) In addition, let j be the output of gate g If v(j) requires all inputs of g to have non-controlling value and a forward implication has contributed to j = v(j), then ( j = v(j)’) => ( i = v(i)’ )

Unique Sensitization Handle the following situations
SOCRATES Handle the following situations The D frontier consists of a single signal All paths from the D frontier to POs pass through distinct gates A signal y is said to dominate a signal x if all directed paths from x to the POs pass through y dom(x) denotes the set of signal that dominate signal x The elements of dom(x) are called dominators of x

Unique Sensitization Instruction 1
SOCRATES Instruction 1 Let x be the only signal the D frontier consists of Let the elements of dom(x) = {y1, y2, ... , yn} be the output signals of their corresponding gates, combined in the set G = {g1, g2, ... , gn} Then for all gates g in G, the non-controlling value is assigned to all those inputs of g that cannot be reached from x A signal y is said to be the immediate dominator of signal x if y dom(x) and y is that element of dom(x) with the lowest circuit level

Unique Sensitization Example D frontier consists of A
SOCRATES Example D frontier consists of A All paths from A go through G G is the dominator of A Distinguish fanins of G between from A and not from A Set D = 1 and E = F = X

Unique Sensitization Example not suitable for previous instruction
SOCRATES Example not suitable for previous instruction A fixed logic should not be assigned to c

Unique Sensitization Instruction 2
SOCRATES Instruction 2 Let x be the only signal the D frontier consists of or a dominator of the only signal D frontier consists of Let x branch out to the gates g1, ... , gn and let all of them require the same noncontrolling value Then the noncontrolling value is assigned to all those signals which branch out to all gates g1, ... , gn This takes care of the previous example This works well in PLA

Improved Multiple Backtrace
SOCRATES Too many fan-out objectives become final objectives, leading to too many nodes in decision tree, resulting in a large number of backtrackings. Initialization flag Set to true when backtrace flag is set to true When the set of current objectives is empty for the first time, examine the set of fan-out objectives, if there does not exit a fault-effect free and conflicting one, reset the initialization flag. Fan-out objectives can become final objectives when initialization flag is true. Satisfy head objectives in the order that sum of 0 and 1-requirement is largest

Multiple Backtrace Objective (s, n0(s), n1(s) ) XOR example
SOCRATES Objective (s, n0(s), n1(s) ) s denotes the number of signals at which the objective occurs n0(s) and n1(s) indicate the number of times the values 0 and 1 are required at s XOR example multi_backtrace_xor2(y, n0(y), n1(y)) { C00 = cost (x1=0, x2=0) ; C01 = cost (x1=0, x2=1) C10 = cost (x1=1, x2=0) ; C11 = cost (x1=1, x2=1) if ( C00 < C11 ) n0(x1) = n0(y) ; n0(x2) = n0(y) else n1(x1) = n0(y) ; n1(x2) = n0(y) if ( C01 < C10 ) n0(x1) = n0(x1)+n1(y) ; n1(x2) = n1(x2)+n0(y) n1(x1) = n1(x1)+n1(y) ; n0(x2) = n0(x2)+n1(y) }

SOCRATES SOCRATES

Dynamic Learning Dynamic Learning All operations performed by the dynamic learning procedure are related to signal values that have already assigned at an earlier stage of the deterministic ATPG Consequently, both learned global implications as well as the uniquely determined logic values have to be recorded in the decision tree and must be rejected, if the respective node of the decision tree should be deleted by backtracking

Dynamic Learning Dynamic Learning If both assignments a=0 and a=1 do not result in a conflict during the implication procedure, the learning is used Example When b=1 and c=1, a=1  h=1 h=0  a=0

Dynamic Learning ( a=0  i=0 )  ( a=1  i=0 )  i=0 Example

Dynamic Learning Dynamic Learning (f=1)  [ a=0  f=0]  a=1 Example

Dynamic Learning Recognition of the necessity of backtracking Example
a = 0 causes conflicts at OR a = 1 causes conflicts at AND Example

Dynamic Learning Dynamic Learning Learning procedure is applied during the test generation process not just in preprocessing step. Improving Implication Learning Concept 1. Dynamic learning of global implications (a) (b)

Dynamic Learning With RTG, FSIM Without RTG, with FSIM

Recursive Learning Example Assume that I1 and J are unjustified
Heuristics Example Assume that I1 and J are unjustified Verify that K=1 is necessary assignment

Recursive Learning Incomplete forward implication
Heuristics Incomplete forward implication No forward implication for D after X=0 has been made However, easy to see that both D=0 and D=1 result in Y=0 X=0  Y=0

Recursive Learning : Definition
Heuristics The gate G is unjustified if there are one or several unspecified input or output signals of G for which it is possible to find a combination of value assignments that yields a conflict at G. Otherwise G is called justified If all consistent combinations of value assignments for which no unjustified gates are left in the circuit, contain the assignment f=V, then the assignment f=V is called necessary. Implications are called precise when they determine all necessary assignments for a given situation of value assignments A set of assignments, J= {f1=V1, … , fn=Vn} where f1 … fn are unspecified input or output signals of an unjustified gate G, is called justification for G, if the combination of assignments in J makes G unjustified.

Recursive Learning : Definition
Heuristics Let Gc be a set of m justifications J1, … , Jm for an unjustified gate G. If there is at least one justification Ji Gc, i = 1,2 … n for any possible justification J* of G, such that Ji  J* , then set Gc is called complete Direct implications are implications which can be performed by only evaluating the truth table for a given gate with a given combination of value assignments at its input and output signals and by propagating the signal values according to the connectivity and timing in the circuit

Recursive Learning : Notation
Heuristics r Integer number which reflects the depth of recursion Set of all unjustified gates as they result from the current state of the test generation algorithm Set of assignments that represents a justification for some gate in a given recursion level r Complete set of justifications for a gate in a given recursion level r Set of unjustified gates in recursion level r as it results from a given justification rmax Maximum recursion depth

Recursive Learning Precise implication initially r=0
Heuristics Precise implication initially r=0 make_all_implications(r, rmax) make all direct implications and set up a list Ur all gates that become unjustified if r < rmax for each gate Gx, x=1,2,in Ur set up list of justifications GxC for each justification JiGxC make the assignments contained in Ji make_all_implications(r+1, rmax) if there is one or several signals f in the circuit, which assume the same logic value V for all consistent justifications JiGxC then learn : (f=V is uniquely determined in level r) make direct implications for all learned values in level r if all justificaitons are inconsistent, then learn: (given situation of value assignments in level r is inconsistent)

Recursive Learning Heuristics Precise implication example

Recursive Learning Fault propagation
Heuristics Fault propagation Fault_propagation_learning(r, rmax) for all signals fDFr successor_signal ==fD while ( sucessor_signal has exactly one successor) fvalue=value of successor_signal successor_signal=successor of successor_signal if (successor_signal is output of inverting gate) value of successor_signal = INV(fvalue) else value of successor_signal=fvalue make_all_implication(r+1, rmax) set up list of new d frontier Fr+1 if ( r<rmax and current sensitization is consistent) fault_propagation_learning(r+1,rmax) if there is one or several signals f in the circuit, which each assume the same logic value V for all non-conflicting sensitizations, then learn: (f=V is uniquely determined in level r) make direct implications for learned values in level r if all sensitizations result in a conflict, then learn: (fault propagation in level r impossible(CONFLICT))

Recursive Learning Heuristics Fault propagation : Example

Recursive Learning Overall System If CONFLICT in optional decision
Heuristics Overall System If CONFLICT in optional decision 1) rmax = 1 2) let f=v be the previous decision 3) assign f=X 4) make_all_implications(0, rmax) 5)fault_propagation_learning(0, rmax) 6) if CONFLICT 7) go to 2) 8) else 9) if f=v’ 10) rmax = 0 11) return to optional decision 12) else 13) rmax++ 14) go to 4)

Implying Node Heuristics A signal line X that cannot be affected by the injected fault is said to be the implying node if the value of X is determined to be the requested level and if the decision implies the value at least one PI Example Logic level 1 is requested for line G during backtrace Value 0 is already assigned to line D G = 1 makes A = B = 0 G : implying node

Implying Node D frontier intercept check Example
Heuristics D frontier intercept check Assigning a controlling value to a selected D frontier so that the fault cannot be propagated through the gate Example (1) D frontier : C, D, E B=0  C=D=E=0 : All paths are intercepted Therefore B must 1 (2) D frontier : F, G D=0  A=C=F=0 E=G=1 : All paths are intercepted Therefore D must 1

Redundancy Identification
Heuristics Test Covering and Fault Dominance f : Z1 s-a-1 g : Y1 s-a-1  Tg = 10 Tg detects f, but f does not dominate g f dominates g if f and g are functionally equivalent under Tg But test covering does not require such functional equivalence If f dominates g, then f also test covers g But converse is not necessarily true

Redundancy Identification
Heuristics Let S be a stem with fanout branch (S1, S2, ... , Sn) If Si is nonreconvergent, then S s-a-v test covers Si s-a-v If Si and Sj reconverge only with equal inversion parities then S s-a-v test covers both Si s-a-v and Sj s-a-v If a stem is redundant, then its nonreconvergent fanout branches and fanout branches reconvergent only with equal inversion parity are also redundant

Test Compaction PI test values are usually partially specified
Combine tests to reduce test length Two tests are compatible if they do not specify opposite values for any PI Two compatible tests Ti and Tj can be combined into one test Tij = Ti  Tj Set of faults detected by Tij is the union of the sets of faults detected by Ti and Tj

Dynamic Compaction Test Compaction Partially specified vector is processed immediately after its generation, by trying to assign PIs with X values so that it will detect additional new faults Procedure Consider a generated test which number of X values is less than a user threshold Select a secondary target fault Try to extend the test to detect the target fault Problems How to select secondary target faults Analyzing the values determined by the partially specified test with the goal of selecting a fault for which ATPG is more likely to succeed When simulating a partially specified vector, critical path tracing also identifies restart gates, which point to areas where additional faults are likely to be easily detected

Static Compaction Test Compaction Postprocessing operation after generating all vectors Too expensive Always yield minimal set Example T1=01X, T2=0X1, T3=0X0, T4=X01 T12=011, T3=0X0, T4=X01 T13=010, T24=001

Test Pattern Compaction
Test Compaction Combinational Test Pattern Generation Algorithm has been advanced to the point that ATPG for million gates designs are possible Advantage of small test set reduce the test application time especially for scan designs storage requirements of test hardware The simple and most effective method of reverse order simulation, which decrease the test size down to 1/3 in many cases Two Test Compaction Methods static compaction dynamic compaction

Test Compaction Inputs values of some tests are partially specified Combine Tests to Reduce Test Length t1 = 01X, t2 = 0X1, t3 = 0X0, t4 = X01 Length 3 Test Set t12 = 011, t3 = 0X0, t4=X01 Length 2 Test Set t13 = 010, t24 = 001

Test Compaction Labeling Fan-out free circuit 1(0) : the value of a line in a test that detects the s-a-0(1) fault on that line ui(zi) : the number of tests in which line i assumes the value 1(0) in a minimum test set. Procedure to label a fanout-free network N 1) Assign (1,1) to PI of N. 2) Let {(zi, ui)} be the set of labels assigned to all inputs {Li} of gate Gs. Assign to the output Ls of Gs the label (zs, us) defined

Test Compaction Labeling Algorithm(fanout free) Network N with minimal test set; essential 0’s and 1’s are underlined. Fanout -free network N.

Test Compaction Labeling Algorithm(nonreconvergent fanouts) Add the numbers of inessential 0’s and 1’s label = (zi, ui, zi’ , ui’) Network Nc With fanout

Test Compaction Maximum Independent Fault Set(MIFS) For every fault f in MIFS, those faults in FFR which can potentially be tested simultaneously with f are associated. l1(6) = {1/0} l1(7) = {4/0} l0(6) = {1/1, 2/1, 3/1} l0(6) = {4/1, 5/1}

Test Compaction COMPACTEST() { preprocessing(); repeat{ select a primary target fault; generate a test for it; /* additional faults in the same FFR are detected */ maximally compact the test; /*compacted test may not be a test for primary */ select a secondary target fault; modify the test to detect it; /* other faults in FFR of the secondary fault are detected */ }until all inputs specified or all faults are tried as secondary randomly specify unspecified inputs; fault simulate the test; }until empty(fault_list) or all faults tried as primary }

Test Compaction Maximal Compaction Each primary input which was set to detect the fault f is complemented and checked if the fault is still detected. If so, it is marked. All such inputs are set to X. Note that the compacted vector covers the original test, but it may not be the test of the fault f.

Test Compaction Rotating backtrace Controllability measures are ignored and a different input line is selected the next time the output of the gate has to be set to the same value

Test Compaction

Sequential Test Generation
Sequential ATPG Generates a sequence of vectors to detect a single stuck-at fault in sequential circuit Controllability and Observability in a sequential circuit are mush worse than those in a combinational circuit Due to the presence of memory elements Search space is too large in general No single strategy/heuristic outperforms others for all applications/circuits Can be combined with low-overhead DFT techniques such as partial scan

Taxonomy highly asynchronous circuits
Sequential ATPG Few approaches can directly deal with the timing issues in highly asynchronous circuits Almost sequential ATPGs neglect circuit delays during test generation

ATPG Levels State Transition Level RTL and Gate Level Gate Level
Sequential ATPG State Transition Level Suitable for pure controllers State transition graphs are either readily available or easily extractable RTL and Gate Level For data dominated circuits Several approaches can effectively use the RTL description for state justification and fault propagation Gate Level Most commercial tools Various approaches Iterative array model Topological analysis algorithms Enhanced from a fault simulator Mixed/hybrid methods : simulation-based + topological-analysis-based Either “Known initial state” or “Unknown initial state”

Sequential ATPG Huffman Model X Z C y D Y Modeling J/K Flip/Flop

Sequential ATPG Iterative Array Model
Conceptually simple Sequential ATPG ALG r=1 repeat { build model with r time frames ignore the POs in the first r-1 frames ignore the q+ outputs in the last frame q(1) = given initial state generate test using “combinational” ATPG if(test found) return (SUCCESS); r=r+1 } return FAILURE

Sequential ATPG Sequential ATPG In Sequential ATPG, multiple time frames are used, hence the target fault is present in every time frame. Error Value Propagates to the faulty line

Sequential ATPG Target fault a s-a-1, initial state q1=q2=0
Time frame 1: q1=q2=0, I(1)=1 propagate the error to q2+. Fault effect not reaches Z, q+ (1)=(0, D) Time frame 2: q1=0, q2=D, D-Frontier={G1, G3, G4}, Select G1 or G4, I(2)=1, q+ (2)=(D, D). Select G3, I(2)=0, q+ (2)=(0, D) Time frame 3: q1=D, q2=D, D-Frontier={Z, G1, G2, G3, G4}, I(3)=1 and Z=D, resulting test sequence is I=(1,1,1)

Sequential ATPG Self Initializing Test r=1, p=0 repeat{
build model with p+r time frames ignore the POs in the first p+r-1 frames ignore the q+ outputs in the last frame if(test generation is successful and every q input in the first frame has value x) return SUCCESS increment r or p }until (r+p=fmax)

Sequential ATPG Self Initializing Test equence Decision Tree
Iterative Array

Sequential ATPG Sequential ATPG Modeling Clock Logic Multiple Clock

Example Known Initial State Example a s-a-1(Time Frame 0) Time Frame 1
Sequential ATPG Known Initial State Example a s-a-1(Time Frame 0) Time Frame 1

Example : continued Known Initial State Example
Sequential ATPG Known Initial State Example Time Frame 2 Time Frame 3

Example Known Initial State Example M s-a-1 Y1=Y2=0 TF 1 TF 2 TF 3
Sequential ATPG Known Initial State Example M s-a-1 Y1=Y2=0 TF 1 TF 2 TF 3

Example Unknown Initial State Example Z s-a-0 TF -1 TF -3 TF -2
Sequential ATPG Unknown Initial State Example Z s-a-0 TF -1 TF -3 TF -2

Sequential ATPG Overview Extended D-Algorithm
Use 9-value logic (0/0, 0/1, 0/X, 1/0, 1/1, 1/X, X/0, X/1, X/X) Convert sequential circuit into iterative logic arrays Trace circuit across space and time both forwards and backwards CONTEST Use concurrent fault simulation and testability measures to derive tests Take into account timing delays STG/BACK Trace across space and time only backwards Keep two time frame states -- last/present state Require less memory

Sequential ATPG Overview INTELLIGEN Based on the STG Algorithm
Automatically select best internal nodes and make them scannable Increase circuit fault coverage by adding Reduced Instruction Scan Paths STALLION Assume a know initial state Extract a state transition table Based on the Modified D-Algorithm Except Propagate faults in forward time Generate test using PODEM Automatically select optimal registers and make them scannable Increase circuit fault coverage by adding Scan registers

Topological Analysis Based
Toplogical Analysis Iterative Array Model Combinational model for sequential circuit Regenerates the feedback signals from previous-time copies of the circuit A rectangle : A copy of the combinational portion of circuits

Iterative Array Model Time frame A copy of the combinational portion of circuit Present state lines : Input of a time frame Primary inputs and the outputs of flip-flops Next state lines : Output of a time frame Primary outputs and the inputs of flip-flops Clock signal is not included in the primary input list in this model Single stuck-at fault in a sequential circuit corresponds to a multiple stuck-at fault in the iterative array model Each time-frame contains a stuck-at fault at fault site

Extended D Algorithm Toplogical Analysis Starts with one copy of the combinational logic and set it time-frame 0 D-algorithm is used for time-frame 0 to generates a combinational test Process When the fault effect is propagated to the next state lines, a new copy of the combinational logic is created as the next time-frame When there are values required at the present state time-frame, a new copy is created as the previous time-frame State justification is then performed backwards in the previous time-frame Continues until there is no value requirement at the present state lines and a fault effect appears at a primary output

Extended D Algorithm : Example
Topological Analysis Time-frame 0 : Fault activation Time-frame 1 : Fault propagation Time-frame -1 : Fault justification Time-frame Time-frame 0 Time-frame 1

Forward time limit : 2 backward time limit : 1 C(0) : y1(0) should assigned X let backward time limit=2 next page

Example (continued) C(-1) : y1 and y2 are X Test : 0011

Nine-Valued Logic Topological Analysis Five-valued logic used in D-algorithm is not appropriate for sequential circuit Due to over specification of the value requirements at some internal nodes Takes into account the possible repeated effects of the fault in the iterative array model Pair of binary values First value : Binary value of the fault free circuit Second value : Binary value of the faulty circuit 0/0, 0/1, 0/X, 1/0, 1/1, 1/X, X/0, X/1, and X/X

Nine-Valued Logic : Example
Topological Analysis Five-valued model mistakenly concludes that there is no 2-vector test due to the conflict at node a in time-frame -1 The required value at present state line y in time-frame 0 is over-specified under the five-valued model 2-vector test : {ab=00, 01}

Nine-Valued Logic : Example

Extended Backtrace Algorithm(EBT)
Topological Analysis Extended D-algorithm and Nine-Valued algorithm Use mixed forward and reverse time processing Disadvantages of mixed time processing May need to maintain a large number of time-frames during test generation because all time-frames are partially processed Implementation is somewhat complicated Reverse Time Processing(RTP) Works backwards in time from last time-frame to first time-frame For a given fault, RTP pre-selects a path from the fault site to a primary output through several time-frames Selected path is then sensitized backwards Backward justification is continued for the required value at the fault site If sensitization process fails, another path is selected

Sequential ATPG Back Algorithm for Sequential Test Generation
D-ALG should be extended to handle multiple fault sites for sequential circuits Sensitized path selection and line justification are multiple decision process, and if conflicts happen, the process should backtrack to another choice. Hence, circuit status has to be stored at every decision point Assuming that forward time processing is done before state justification the circuit status must contain at least M time frames.

Topological Analysis Advantages of Reverse Time Processing At any time-frame, only two time-frames need to be maintain Current time-frame and previous time-frame Low memory usage and easy implementation Decision points and their corresponding circuit status still need to be stacked for the purpose of backtracking It is easier to identify repetition of state requirement State repetition State requirement has been visited earlier during the current backward justification process : Loop in the state transition diagram By recording the state requirement after backward justification of each time-frame and comparing each newly visited state requirement with the list of previously visited state requirements Backward justification process should not continue to circle that loop and backtracking should take place immediately Similarly, can maintain a list of illegal states

Topological Analysis Major Problems Only single-path is selected for sensitization Faults that require multiple-path sensitization for detection may not be covered The number of possible paths from the fault site to the primary outputs is very large Trying path by path is not practical

Sequential ATPG 9 Value D-ALG EBT(Extended Backtrace) Sequential ATPG
Gives up forward process by allowing no choice on sensitizing path selection. Backward process from the sensitized P.O. All requirements for one time frame handled simultaneously For all sequential as well as combinational ckt elements, output values can be justified by current time frame and previous time frame status. Many paths are tried using a diagram composed of many paths

Back Algorithm Improvement of the EBT algorithm
Topological Analysis Improvement of the EBT algorithm Instead of pre-selecting path, BACK algorithm pre-selects a primary output Assigns a D or D’ to the selected primary output and justifies the value backwards Testability measure(called drivability) is used to guide the backward D-justification from selected primary output to fault site Drivability Based on SCOAP controllability measurement of both fault-free and faulty circuits Uses Fault injection technique Instead of using a bit flag with each signal indicating whether the signal is a stuck-at faulty, extra 2-input gate is inserted into the circuit for injecting a fault s-a-0(1) : 2-input AND(OR) gate is inserted and the values of extra primary input is hardwired 1/0(0/1) All gates can be treated equally & it eliminates need for flag checking

Sequential ATPG BACK Algorithm
1. Calculate the good controllability measure. 2. Pick a target fault and calculate the bad machine controllability measurement and the derivability measure. 3. Based on the derivability measurement, select a primary output to have a sensitized value. If no primary output is available, this fault is not testable. Set the current time frame as t=0. 4. Justify all the values required at the current time frame. If no conflict happens, go to Step 5. Otherwise, change the latest choice and set the current time frame to be the time when the choice was made. Go to Step 4. If no choice left, go to Step 3. 5. If state requirement matches the initial state or no requirement, stop . Otherwise, set the previous time frame as the current time frame and go to Step 4.

Back Algorithm Require smaller memory space Efficient than EBT
Sequential ATPG Require smaller memory space Efficient than EBT number of POs < number of paths

Sequential ATPG SPLIT circuit model
The SPLIT model is an enhanced 9-value model, where each of good machine signal line and faulty machine signal line has 0, 1, X. In addition, the relation between two machine out of {UNKNOWN, DIFFERENCE, EQUIVALENCE} is kept. If the relation is DIFFERENCE, the derivability measure is used for justification; otherwise the controllability measure is used. Result Faults Time Detected Untestable Dropped Efficiency s

Sequential ATPG Sequential ATPG HITEC Forward time processing to activate the fault and propagate the fault effect over multiple time frames Backward time processing to justify state requirements of flip-flops 9 Value logic system is used. Dynamically adjustable window size, when more time frames than the window size is needed, scroll over. Use the concept of targeted D-Frontier to choose a target D element and determine the dominators w.r.t that element only. Use of good circuit state knowledge Use of fault simulation knowledge

HITEC 1st Phase : Forward Time Processing
Topological Analysis 1st Phase : Forward Time Processing Fault activation Fault propagation Employs dominators, unique sensitization, and mandatory assignments used in combinational ATPG No drivability is needed Computing time is further saved 2nd Phase : Reverse Time Processing Justification of the initial state determined in the 1st phase

FASTEST Only Forward Time Processing
Topological Analysis Only Forward Time Processing Uses PODEM as underlying test generation algorithm Pre-processing Estimates the total number of time-frames required for detection Also estimates at which time-frame the fault is activates Based on SCOAP-like controllability and observability measures Iterative array model with estimated number of time-frames Procedure Present state lines of the very first time-frame : unknown values Initial objective : activation of target fault at estimated time-frame Backtraces starting from the line of the initial objective until it reaches an unassigned primary input or a present state line in the first time-frame For the latter case, backtracking is performed immediately If algorithm fails to find test, the number of time-frame increased

FASTEST Comparison with RTP
Topological Analysis Comparison with RTP Not waste time justifying unreachable states Usually generates a shorter justification sequence for bringing the circuit to a hard-to-reach state Forward time processing algorithm requires a good estimate of the total number of time-frames and the time-frames for activating each target fault

Sequential ATPG Using simulation knowledge Using good circuit state

Sequential ATPG Sequential ATPG

Practical Issues Multiple-clock and/or multiple-phase designs
Topological Analysis Multiple-clock and/or multiple-phase designs Treat the clock signals as part of the primary input signals Converting an edge-triggered flip-flop into a model that consists of delay elements and gates Combinational loops A set of feedback connections whose removal will eliminates all combinational feedback loops is first identified At each of these combinational feedback lines, a pseudo delay elements is inserted For the time-frames in which at least one PPS(Pseudo present state)/PNS(Pseudo next state) line pair does not have consistent binary values, each PS/NS line pair is forced to have the same binary value and the primary inputs are not allowed to change values If a PPS/PNS line pair does not have consistent values, the actual value at the corresponding combinational feedback line has not stabilized yet, so the clock should not be applied and the primary input vector should not be changed

Practical Issues Test efficiency
Topological Analysis Test efficiency Determining the set of undetectable faults is also an objective of sequential test generation The ratio of the number of detected faults plus the number of identified undetectable faults to the total number of faults Robust test for asynchronous preset/clear line and for buses No hazards or glitches are allowed at asynchronous preset/clear lines Stable and inactive signal values must be maintained at asynchronous preset/clear lines Generated Test Sequence should not cause bus contention or leave the bus floating

Complexity Sequential depth Maximum number of flip-flops encountered in any path from a primary input to primary output Number of sequential cycles Sequential cycle exist if a flip-flop’s data input is in the fanout cone of the flip-flop’s output Maximum length of any sequential cycle Length of a cycle is defined as the number of flip-flops in the feedback loop Density encoding The ratio of the number of valid states to the total number of states Key indicator of topological-analysis-based sequential ATPG

Sequential Undetectability Formal and precise definition of undetectability with respect to four different test strategies Full-scan Undetectable if combinationally undetectable Hardware reset is available Undetectable if no input sequence exists such that the output response of the fault-free circuits is different from the response of the faulty circuit, both starting from their reset Single observation time(SOT) Sequence detects a fault only if a fault effect appears at the same primary output and the same vector for all power-up initial state-pairs of the fault-free and faulty circuits Most gate-level algorithms assume the SOT test strategy Multiple observation time(MOT) Fault can be detected by multiple input sequences each input sequence produces a fault effect at some primary output for a subset of power-up initial state-pairs and the union of the subsets cover all possible power-up initial state-pairs

SOT undetectable MOT detectable : Example Under SOT No input sequence can produce a 1/0 of 0/1 Under MOT, AC=(11,00) If initial state X/0 Output response of st vector is 1/0 If initial state X/1 Output response (1/1, 0/1) Advantages of MOT strategy Undetectable under SOT, but detectable under MOT MOT test is shorter that the SOT test in general Full initialization may not be necessary

Sequential Redundancy Defined with respect to three possible modes Reset mode Reset to a specific initial state at the beginning of operation Synchronization mode Operation starts with a specific initialization sequence No-synchronization mode Operation starts from the state in which circuit happens to be A fault is redundant under a given mode operation if the fault does not change the expected output response Relationship between Undetectability & Redundancy Partial test Input sequence such that for at least one initial state of the faulty circuit, the output response of the faulty circuit is different from the response of the fault-free circuit A fault is redundant iff it is not partially detectable

Simulation-Based Approaches
Enhanced from a logic simulator or a fault simulator Combination of simulation and cost function guidance Procedure Based on the previous tests, a new trial vector or a trial sequence is generated Logic simulation or fault simulation is then performed From the simulation result, a cost function that determines how far the state of the circuit is from the required state for the detection of the fault(s) is computed If the cost is reduced, the new trial vector/sequence will be included in the final sequence; otherwise it will be discard A new trial vector is then generated and the process repeats until the fault is detected or the number of trial vector reaches a pre-specified limit

SOFTG Simulation Based To ensure hazard free tests, SOFTG generates a test sequence in which each vector differs from its previous vector in one bit Uses fault simulator for all forward signal propagation Backtrace of PODEM is used to find the best input bit to be flipped Not cause races or hazards in the fault-free circuit

CONTEST Enhanced from concurrent fault simulator
Simulation Based Enhanced from concurrent fault simulator Generates a new trial vector by changing a single bit in the last accepted vector Initial phase to bring flip-flops into known states irrespective of the starting state Cost function is the number of uninitialized flip-flops Concurrent fault detection phase generate tests by targeting all undetected faults concurrently Cost function is the minimum distance of any fault effects created by this fault to any primary output Single fault detection phase Cost function is based on SCOAP-like testability measure Take into account timing delays Trace circuit across space and time only forwards

Using Genetic Algorithm
Reproduction Copying potentially useful candidate vectors and sequence Mutation Flipping bits in a vector Splicing of vectors Producing a new sequence from subsequences of existing sequences CRIS, GATTO Cost functions Distance of the fault effects to the primary outputs Distribution of the switching activity of the previously generated tests Increasing the switching activity in an inactive subcircuit would increase the probability of detecting faults in that subcircuit

Using Genetic Algorithm
GATEST Cost(fitness) function to maximize the number of faults detected and the number of fault effects propagated to flip-flop Several genetic algorithm parameters are important in achieving good results population size, the number of generations for evolving the vectors, and the crossover and mutation probabilities in evolving the vectors

Simulation-Based Approaches
Genetic Algorithm Advantages Logic simulation and fault simulation deal with circuit delays in a very natural way Even highly asynchronous sequential circuits can be handled Because a fault simulator can accept transistor-level netlist, it can handle transistor-level fault model Less CPU time than iterative array model Disadvantages Cannot identify undetectable faults May also fail to generate tests for certain hard-to-active faults Test sequence generated tends to bee longer than that generated by the array-modeled-based approach

Hybrid Approaches Hybrid Combination between the simulation-based techniques and topological-analysis-based techniques CRIS-hybrid When CRIS generates a fixed number of test vectors without improving fault coverage, array-model-based test generation is applied to get a set of vector to be added to both the final test sequence and the current population to be used for trial vector generation for further call to CRIS Array-model-based test generation is also used to identify undetectable faults GA-HITEC Topological algorithm For fault excitation and fault propagation Genetic algorithm State justification

Approaches with Known Reset State
Sequential ATPG Valid for controllers usually have a hardware reset STALLION Extracts the state transition graph for fault-free circuit Sequence may corrupted by the fault Fault simulation is required Based on PODEM and iterative array model STEED Generates ON-set and OFF-set for primary output and each next state line for the fault-free circuit VERITAS BDD-based test generator Preprocessing phase to compute the state transition information Fails due to memory explosion for designs with hundreds of flip-flops

Conclusion Combinational ATPG Sequential Approaches
Various and huge researches have been reported Can generates high quality tests efficiently Few problems remain in combinational ATPG fields Sequential Approaches Due to the high complexity, remains a challenging task Some test generators combined with Design for Testability technique have shown a certain success in testing large sequential circuit

Fault Classes in Synopsys
detected A pattern detects this fault tied (high or low) This class of fault cannot be tested because it is connected to logic 1 (tied high) or logic 0 (tied low). ATPG cannot detect stuck-at-1 or stuck-at-0 faults on this node and other nodes that it controls redundant ATPG cannot generate a test for this fault because the overall static behavior of the circuit is independent of the values at this node untested A fault is untested if the value at a node cannot be controlled or observed. When a node cannot be controlled or observed, ATPG cannot generate a test pattern to detect the fault. TestSim marks a fault untested if not detected by the vector set that is simulated.

abandoned A fault in this category indicates that ATPG has reached the limit that you set for computer resource allocation for the particular fault and was unable to generate a pattern-possibly because of a design rule violation. Even with additional computer resources, ATPG may not automatically generate a pattern for the particular fault probable detect TestSim marks a fault as a probable detect if, during fault simulation, a circuit has an unknown value at an observable output or scan-out and the fault-free circuit has a known value. Probable detects usually occur for faults on clock lines, reset lines, and enable lines.

hyperactive During fault simulation, some faults have a high computational cost, and thus are very expensive to fault simulate. Sometimes the fault is hypertrophic, which means that too many fault effects have diverged from the fault, and memory limitations become an issue. Sometimes the fault is hyperactive, which means the fault activity is too extensive. These faults are collectively called hyperactive faults. Oscillating During fault simulation, some faulty circuits begin oscillating. When a fault is marked as oscillating, it is removed from fault simulation. dont_fault The faults belonging to this class are the faults that were not considered in this test program no_status Faults with the no_status designation are faults whose status has not yet been determined.

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