1. A Data Stack CoreGen
Discussion 12.1

2. Example of the need for a stack

4. A 32 x 16 Stack

5. A 32 x 16 Stack Module

6. stack_ctrl32 wr_addr rd_addr 00000 11111 entity stack_ctrl is port (
clr: in STD_LOGIC;
clk: in STD_LOGIC;
push: in STD_LOGIC;
pop: in STD_LOGIC;
we: out STD_LOGIC;
amsel: out STD_LOGIC;
wr_addr: out STD_LOGIC_VECTOR (4 downto 0);
rd_addr: out STD_LOGIC_VECTOR (4 downto 0);
full: out STD_LOGIC;
empty: out STD_LOGIC );
end stack_ctrl;
00000
wr_addr
rd_addr
11111

7. stack_ctrl32 architecture stack_ctrl_arch of stack_ctrl is
architecture stack_ctrl_arch of stack_ctrl is
signal full_flag, empty_flag: STD_LOGIC;
begin
stk: process(clr, clk, push, pop, full_flag, empty_flag)
variable push_addr, pop_addr: STD_LOGIC_VECTOR(4 downto 0);
if clr = '1' then
push_addr := "11111";
pop_addr := "00000";
empty_flag <= '1';
full_flag <= '0';
wr_addr <= "11111";
rd_addr <= "00000";
full <= full_flag;
empty <= empty_flag;

8. stack_ctrl32 wr_addr rd_addr 00000 elsif clk'event and clk = '1' then
11111
rd_addr
wr_addr
elsif clk'event and clk = '1' then
if push = '1' then
if pop = ‘0' then
if full_flag = '0' then
push_addr := push_addr - 1;
pop_addr := push_addr + 1;
empty_flag <= '0';
if push_addr = "11111” then
full_flag <= '1';
push_addr := "00000";
end if;
else
–- write to top of stack (pop_addr) without pushing
-- don’t change push_addr and pop_addr

9. stack_ctrl32 wr_addr rd_addr elsif pop = '1' then 00000
if empty_flag = '0' then
pop_addr := pop_addr + 1;
if full_flag = '0' then
push_addr := push_addr + 1;
end if;
full_flag <= '0';
if pop_addr = "00000" then
empty_flag <= '1';
wr_addr <= push_addr;
rd_addr <= pop_addr;
00000
11111
rd_addr
wr_addr

10. stack_ctrl wr_addr rd_addr 00000 full <= full_flag;
11111
rd_addr
wr_addr
full <= full_flag;
empty <= empty_flag;
if push = '1' and full_flag = '0' then
we <= '1';
else
we <= '0';
end if;
if push = '1' and pop = ‘1' then
amsel <= '1';
amsel <= '0';
end process stk;
end stack_ctrl_arch;

11. A 32 x 16 Stack Module

12. library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity stack32x16 is
port (
d: in STD_LOGIC_VECTOR (15 downto 0);
clr: in STD_LOGIC;
push: in STD_LOGIC;
pop: in STD_LOGIC;
clk: in STD_LOGIC;
q: out STD_LOGIC_VECTOR (15 downto 0);
full: out STD_LOGIC;
empty: out STD_LOGIC );
end stack32x16;

13. architecture stack32x16_arch of stack32x16 is
component stack_ctrl
port(
clr : in std_logic;
clk : in std_logic;
push : in std_logic;
pop : in std_logic;
we : out std_logic;
amsel : out std_logic;
wr_addr : out std_logic_vector(4 downto 0);
rd_addr : out std_logic_vector(4 downto 0);
full : out std_logic;
empty : out std_logic);
end component;

14. component mux2g
generic(
width : POSITIVE);
port(
a : in std_logic_vector((width-1) downto 0);
b : in std_logic_vector((width-1) downto 0);
sel : in std_logic;
y : out std_logic_vector((width-1) downto 0));
end component;
component dpram32x16
port (
A: IN std_logic_VECTOR(4 downto 0);
CLK: IN std_logic;
D: IN std_logic_VECTOR(15 downto 0);
WE: IN std_logic;
DPRA: IN std_logic_VECTOR(4 downto 0);
DPO: OUT std_logic_VECTOR(15 downto 0);
SPO: OUT std_logic_VECTOR(15 downto 0));

15. signal wr_addr, rd_addr : std_logic_vector(4 DOWNTO 0);
signal we, amsel: std_logic;
constant bus_width: integer := 5;
begin
mem1 : dpram32x16
port map (
A => wr2_addr,
CLK => clk,
D => d,
WE => we,
DPRA => rd_addr,
DPO => q,
SPO => open);

16. mux2: mux2g generic map(width => bus_width) port map
(a => wr_addr,b => rd_addr, sel => amsel, y => wr2_addr);
sa1: stack_ctrl port map
(clr => clr, clk => clk, push => push, pop => pop,
we => we, wr_addr => wr_addr, rd_addr => rd_addr,
full => full, empty => empty, amsel => amsel);
end stack32x16_arch;