1. DESIGN FOR MANUFACTURABILITY

2. DUMMY POLY
Severe distortion
Reduced distortion

3. Dummy gates for increased manufacturability
DUMMY POLY
Dummy gates for increased manufacturability

4. Dummy gates induce spared silicon area
Active gate
Active gate
Dummy gate
Unused
area
Dummy gates induce spared silicon area

5. Some nano-CMOS require 2 dummy gates per cell (Intel 14-nm)
Shared dummy gates reduce the cell area (Intel 10-nm)
10 nm technology leadership, KAIZAD MISTRY, TECHNOLOGY AND MANUFACTURING DAY, 2017

6. DUMMY GATES
Shared Dummy
gate
Active gate
Active gate

7. For pitch lower than 80nm (M2-M8): simple patterning
DOUBLE PATTERNING
For pitch lower than 80nm (M2-M8): simple patterning
For pitch lower than 80nm (M1-M2): double patterning

8. After fabrication in single patterning
DOUBLE PATTERNING
Initial M1 layer
6 λ minimum pitch
Bridge
After fabrication in single patterning
Open

9. 66 nm pitch M1 patterns need double patterning
Second patterning
First patterning

10. Ion Ion Ioff Ioff FINFET MANUFACTURABILITY
Fins should be aligned and horizontal, regular pitch 6  (1+5)
Non-aligned fins may lead to gate distortion and current performance spread
Ion
Ion
Ioff
Ioff

11. FINFET MANUFACTURABILITY
Gates should be aligned and vertical, regular pitch with 8  minimum (2+6)

12. Nearly manufacturable Not manufacturable
STUDENT DESIGNS
Nearly manufacturable
Not manufacturable
ALU project by Master students INSA, 2016
SRAM project by Master students INSA, 2016