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ECNG1006 – Digital Component
Design Project Helps “The Frequency Meter”
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Objectives of Project This project investigates the digital design and implementation of a Frequency Meter using the Xilinx Schematic Editor
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Complete System
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Frequency Determination Unit
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Changes Made The ‘dataout’ of the modulo 4 counter is now 2 bits wide(00->01->10->11->00) The ‘dataout’ of the modulo 4 counter is now connected to the ‘select’ of the 4x4bits multiplexer LUT has to be re-done to match this change
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Frequency Meter Display Unit
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BCD to 7-Segment Converter
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Design of circuit for Segment G
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Design of circuit for Segment G
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Design of circuit for Segment G
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Implementation of circuit for Segment G
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Changes were made to the following slides to match Display Unit Design changes made!!!!!!
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Multiplexers – 4x1bit
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Multiplexers – 4x1bit(design)
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Multiplexers – 4x4bits(design)
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Demultiplexers – 4x1bit
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Demultiplexers – 4x1bit(design)
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Demultiplexers – 4x4bits(design)
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THE END
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