1. Implementation Example - DSP based Adaptive Array Antenna System -
Fire Tom Wada
Professor, Information Engineering, Univ. of the Ryukyus
2018/11/30
System Arch (Fire Tom Wada)

2. DSP based Adaptive Array Antenna System
DSP based AAA System for OFDM receiver is shown as a implementation example.
The System is composed of three parts.
OFDM demodulator
Adaptive Array Antenna
DSP
2018/11/30
System Arch (Fire Tom Wada)

3. System Arch 2008 (Fire Tom Wada)
OUTLINE
ISDB-T abstract
OFDM demodulator
Adaptive Array Antenna System
System Design
2018/11/30
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4. Terrestrial Digital TV in Japan
BST-OFDM
segment
Modulation:
64QAM, 16QAM, QPSK
5.6MHz
Power
Number of sub-carrier
192(Mode2) / 384(Mode3) 1 13
We’ve adopted BST-OFDM which is divided 5.6Mhz into 13 segments.
There are 3 types of modulations 64QAM, 16QAM and QPSK.
Feature of OFDM is ……………..
Because of that, inter-symbol ……………..
Frequency
Inter-symbol interference is eliminated
Multi-path distortion to be reduced
Long symbol duration composed by
sub-carriers with a guard time
The feature of OFDM
2018/11/30
System Arch (Fire Tom Wada)

5. Today’s Broadcast (ISDB-T)
HDTV
Broadcast
Handheld
64QAM
(13segment)
QPSK
(1segment)
Modulation
15Mbps
370Kbps
Data Rate
Transmission Data Rate is ..
64QAM is for HDTV Broadcast which need 13segment types of OFDM ,
QPSK is for Handheld Broadcast which need 1segment Type of OFDM
- HDTV broadcast has already started since 2003, but currently only for home-use,
and Handheld SDTV broadcast will be planed to start this year.
*****
The 13 segments can supply high quality but it has difficulty on mobility.
1segment type OFDM LSI can supply the high mobility, but quality is not so high.
We have no Mobile digital HDTV receiver so far.
2003
Availability
2005/E
Mobile
Home-use
Usage
High / Low
Quality/Mobility
Low / High
2018/11/30
System Arch (Fire Tom Wada)

6. Simplified OFDM Receiver ModelA D C
Symbol
Reform F T E Q
Channel
Estimator
Synchronizer F T
Channel
Estimator
Synchronizer
Which part we are Focusing On?
1st Click
Pick Up 3 Technical Areas where we attach importance to for mobile application.
2nd Click
Highlight Channel Estimation.
Accurate and Agile Synchronizer
Broad Dynamic Range of FFT
Sophisticated Channel Estimation
2018/11/30
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7. Guard Interval of OFDM signal
In order to prevent (n-1) delay symbol from interfering to n symbol, GI is pre-appended as a copy of the tail of the Effective OFDM symbol.
We call Head-GI and Tail-GI.
Head-GI and Tail-GI will be used in the AAA signal processing.
Effective OFDM symbol=1 / f0 Tg Tg
Tail GI
Head GI
COPY
Data: 8K points
8704 points
Mode3:GI(1/16) ＋
GI: points
2018/11/30
System Arch (Fire Tom Wada)

8. Adaptive Array Antenna
Using multiple Antenna, signals are combined to reproduce a clean signal .
Complex multiply and complex addition is used.
DSP to calculate those weights (wn).
Desired Signal
combined ？
Delayed
Noisy
Interference
2018/11/30
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9. Using DSP, Coefficients are calculated
AAA signal processing
Using DSP, Coefficients are calculated
K-elements
Antennas
Combined Output
Sample Output Signals
(Tail GI period)
Sample Input Signals
(Head GI period)
2018/11/30
System Arch (Fire Tom Wada)

10. Since the algorithm should be flexible, S/W approach is better!
Adaptive Algorithms
Asynchronous
Maximum Ratio Combining_Asyn
Synchronous
Maximum Ratio Combining_Syn
Sample Matrix Inversion
Power Inversion
Wave
Adaptive Beam- forming
Adaptive Null Steering
1. MRC_ASYN
ANY ○ ×
2. MRC_SYN
OFDM
3. SMI
4. PI
Adaptive Beam-forming
Emphasize the desired Signal
Adaptive Null Steering
Suppress interference signal
Since the algorithm should be flexible, S/W approach is better!
2018/11/30
System Arch (Fire Tom Wada)

11. MRC(Maximum ratio combining)
Coefficients are calculated by cross-correlation of input signals and combined signal.
MRC_ASYN
MRC_SYN
Head_GI = Tail_GI property is used.
symbol
cross correlation
combined
OFDM symbol
cross correlation
combined
Tail GI
Head GI
2018/11/30
System Arch (Fire Tom Wada)

12. SMI(Sample Matrix Inversion)
SMI needs reference signal
Here Head_G I= Tail_GI property is used.
OFDM symbol
cross correlation
Head GI
auto correlation
inversion
combined
Tail GI
2018/11/30
System Arch (Fire Tom Wada)

13. System Arch 2008 (Fire Tom Wada)
PI(Power Inversion)
PI algorithm can suppress maximum signal. =( Power Inversion)
Here, we try to suppress the Difference of Head_GI and Tail_GI.
OFDM symbol
Head GI
auto correlation
inversion －
Tail GI
2018/11/30
System Arch (Fire Tom Wada)

14. System Arch 2008 (Fire Tom Wada)
Evaluation Condition
Base signal
Angle of Arrival
Delay [㎲]
Power [dB]
Signal #1
DTV28CH
-30
Signal #2 15
3/8 * Tg
Signal #3
-75
6/8 * Tg
Signal #4 60
9/8 * Tg
Interferenece
Delay
Desired
-75°
AAA-OFDM SYSTEM
60°
15°
-30°
DSP Board
DSP
interface
Host PC
Weight data
Beam Pattern
2018/11/30
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15. MATLAB Simulation [MRC_ASYN, MRC_SYN)]
Adaptive Beam-forming
MRC_ASYN
MRC_SYN
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16. MATLAB Simulation [SMI,PI]
Adaptive Beam-forming
Adaptive Null Steering
SMI PI
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17. System Arch 2008 (Fire Tom Wada)
SYSTEM DESIGN
Reflec-tion etc.
OFDM
receiver
Adaptive
processor
DSP
interface GI
Tuner
Complex data
2018/11/30
System Arch (Fire Tom Wada)

18. Sample Head&Tail GI signal
DSP based AAA System
Sample Head&Tail GI signal
C6713DSP Floating Point DSP
225MHz
(1350MFLOPS)
2018/11/30
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19. TMS320C6713 DSP [Texas Instruments Inc, Floating point DSP]
Head GI
EMIF
Tail GI
512points * 4branches
C6713DSP
225MHz (1350MFLOPS)
Internal Memory
Program Area：4KB
Data Area：4KB
SRAM：192KB
EXT_HWI[1-3]
GPIO
DSP_RUN DSP_VALID
Peripheral
32bit EMIF
GPIO
Host PC
2018/11/30
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20. CLK error compensation
1 antenna OFDM Receiver
IFFT EQ
BaseBand Conversion
CLK error compensation
RF error compensation
Complex data
SYNC
FFT
Tuner
A/D
TMCC CR
D/A
AGC
2018/11/30
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21. 4 antenna DSP based AAA OFDM receiver
IFFT EQ
SYNC
BaseBand Conversion
CLK error compensation
RF error compensation
A/D
Complex data
FFT
Tuner
A/D
TMCC
A/D CR
A/D
D/A
AGC
Head & Tail GI 4branches
Weight data
DSP Interface
TMS320
C6713 DSP
2018/11/30
System Arch (Fire Tom Wada)

22. System Arch 2008 (Fire Tom Wada)
DSP Interface
From 4 Branch Signal
To Weight
DSP interface
DSP Controll Logic
Write Data Logic
Buffer RAM
Parameter 4w x 32b
FF 4w x 32b
Y0C[0:511]
RESET
EXTHWI1-3
BkSel2
VALID
DSP_RUN
Y1C[0:511]
BRAMC 8kw x 32b
Y2C[0:511]
Y3C[0:511]
Signal Transfer Logic
DSP Board
GP_IO
CE2
CE1
SDRAM (option)
FLASH
TI DSP
C6713
CLK
LED
DIP
2018/11/30
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23. H/W – S/W interface timing diagram w/o DMA
ASYNC mode
CPU is used for Data transfer
SYNC mode
2018/11/30
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24. Performance Optimization
Let processor core to concentrate weight calculation!
EDMA (Enhanced Direct Memory Access)
CPU core is free for Data transfer
Double memory buffer in DSP
EDMA memory access does NOT conflict with CPU core memory access.
2018/11/30
System Arch (Fire Tom Wada)

25. Double Buffer 2 bank Ping-Pong buffer
2-port RAM is used for Real Implementation.
Each Port can operate at Different CLK frequency.
Ping
Pong
2-port BRAM
Writer (OFDM receiver)
Reader (DSP)
Writer access to Pong Buffer
2018/11/30
System Arch (Fire Tom Wada)

26. H/W – S/W interface timing diagram
Data Transfer during CPU
2018/11/30
System Arch (Fire Tom Wada)

27. Before Optimization EMIF TMS320 C6713DSP X0Br1[0-511] X0Br2[0-511] 1
Head GI
Head GI
Head GI transferred using CPU
X0Br1[0-511]
X0Br2[0-511]
X0Br3[0-511]
X0Br4[0-511] 1
Tail GI transferred
using CPU
Tail GI
TMS320 C6713DSP
Tail GI
X1Br1[0-511]
X1Br2[0-511]
X1Br3[0-511]
X1Br4[0-511]
MRC ASYN
MRC SYN
SMI PI 1
ISRAM address 11
CPU Data Transfer
parameter
Parameter
Weight
Weight data
W0Br1
W0Br2
W0Br3
W0Br4
2018/11/30
System Arch (Fire Tom Wada)

28. System Arch 2008 (Fire Tom Wada)
After Optimization
EMIF
EDMA
Head GI
Head GI
Head GI Received
Channel
X0Br1[0-511]
X0Br2[0-511]
X0Br3[0-511]
X0Br4[0-511] 1 1
Head GI Received
Channel
Tail GI 1
Ping Buffer
Pong Buffer
TMS320 C6713DSP
Tail GI
X1Br1[0-511]
X1Br2[0-511]
X1Br3[0-511]
X1Br4[0-511]
MRC ASYN
MRC SYN 1
ISRAM address
SMI PI 12
Ping Buffer
Pong Buffer
parameter
Parameter
Weight
Weight data
W0Br1
W0Br2
W0Br3
W0Br4
2018/11/30
System Arch (Fire Tom Wada)

29. System Arch 2008 (Fire Tom Wada)
CPU Speed Comparison
ASYNC mode
SYNC mode
MRC_ASYN
MRC_SYN
SMI PI
Before
343.58㎲
364.99㎲
470.19㎲
413.98㎲
After
147.54㎲
173.64㎲
268.15㎲
223.95㎲
Improvement
57.06%
52.43%
42.97%
45.90%
1 EDMA per Symbol
2 EDMA per Symbol
MAX 57% Speed Enhancement
2018/11/30
System Arch (Fire Tom Wada)

30. Measured Results [MRC_ASYN, MRC_SYN)]
BER: 1.30E-02
BER: 4.3E-03
2018/11/30
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31. Measured Results [SMI,PI]
BER: 6.60E-03
BER: 2.40E-03
2018/11/30
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32. System Arch 2008 (Fire Tom Wada)
SYSTEM PHOTOGRAPH
4 antenna
TUNER
AGC
ADC
DSP board
Video
JTAG Emulator
2018/11/30
System Arch (Fire Tom Wada)

33. System Arch 2008 (Fire Tom Wada)
ALL SUBJECTS ARE FINISHED!
THANK YOU!!!
2018/11/30
System Arch (Fire Tom Wada)