1. Memory

2. Memory Decoders

3. Array-Structured Memory

4. Array Decoding

5. Hierarchical Memory Arrays

6. Memory Timing Definitions

7. Memory Timing Approaches

8. Example: HM6264 8kx8 SRAM

9. HM6264 Interface

10. Function Table

11. Timing

12. Read Cycle 1

13. Read Cycle 1 85ns min 85ns max 85ns max 10ns min 30ns min 85ns max

14. Read Cycle 2

15. Read Cycle 2
85ns max
10ns min
10ns min

16. Write Timing

17. Write Cycle

18. Write Cycle 85ns min 75ns min 0ns min 75ns min 55ns min 0ns min
0ns min, 30ns max
40ns min
0ns min

19. What Does All This Mean For a read: For a write:
If you assert CS1, CS2, address, and OE all at the same time, it will be max 85ns before valid data are available at chip outputs
For a write:
You can assert CS1, CS2, address, data, and WE all at the same time if you want to
You need to wait 55ns from WE edge, or 75ns from CS1/CS2 edge for write to have happened

20. R/W Memories In General

21. SRAM Circuits

22. SRAM Cell, Transistors

23. SRAM, Resistive Pullups

24. Array-Structured Memory

25. Memory Column
Each column has all the support circuits

26. Reading the Bit Single-ended read using an inverter
Dynamic pre-charge on the bit lines
P-types pull bit lines high

27. Reading the Bit 2 Single-ended read using an inverter
Dynamic pre-charge on the bit lines
Note the N-types used as pull-ups

28. Reading the Bit 3 Differential read using sense amp
Static N-type pullup on the bit lines

29. Read Waveforms

30. Sense Amp

31. Sense Amp Transistors

32. Column Organization

33. Write Circuits

34. Write Circuit Simulation

35. Analog Sim, Circuit

36. Analog Analysis, Write

37. Analog Analysis, Read

38. 6T SRAM Layout

39. Another 6T SRAM Layout

40. SRAM bit from makemem (v1)

41. SRAM bit from makemem (v2)

42. Array-Structured Memory

43. Row Decoders Select exactly one of the memory rows
Simple versions are just gates

44. Row Decoder Gates Standard gates
Or, pseudo-nmos gates with static pull up
Easier to make large fan-in NOR

45. Pre-decode Row Decoder
Multiple levels of decoding can be more efficient layout

46. Pre-decode Row Decoder
Other circuit tricks for building row decoders…

47. Array-Structured Memory

48. Array-Structured Memory

49. Sharing Sense Amps

50. Sense Amp Mux

51. Sense Amp Mux

52. Decoded Column Decode

53. Improving Speed, Power

54. Multi-Port Memory Very common to require multiple read ports
Think about a register file, for example

55. Multi-Port Register
Re1
Re0
Slightly larger cell, but with single-ended read – makes a great register file

56. Register File
Slightly larger cell, but with single-ended read – makes a great register file

57. Dynamic RAM Get rid of the pull-ups! Store info on capacitors
Means that stored information leaks away

58. Dynamic RAM…
Once you agree to use a capacitor for charge storage there are other ways to build this…

59. 3T DRAM Circuit

60. 3T DRAM Layout
BL2
BL1
GND
RWL M3 M2
WWL M1

61. 1 T DRAM Circuit

62. 2-T (1-T) DRAM layout
Note the increased gate size of the storage transistor
Increases the capacitance

63. 1T DRAM Observations

64. 1T DRAM Read/Write

65. 1T DRAM Cell
“Folded bit line”

66. Array of DRAM Cells
“Folded
Bit
Line”

67. Reading a 1T DRAM Cell
Charge Sharing

68. DRAM Sense Amp

69. Photo of 1T DRAM

70. Advanced DRAM Cells Try to get more capacitance per unit area…
Trench Capacitor

71. Examples of Advanced DRAMs
Word line
Cell plate
Capacitor dielectric layer
Insulating Layer
Cell Plate Si
Capacitor Insulator
Transfer gate
Isolation
Refilling Poly
Storage electrode
Storage Node Poly
Si Substrate
2nd Field Oxide
Trench Cell
Stacked-capacitor Cell

72. Memory Timing Approaches

73. DRAM Interface

74. Extended Data Out Page Mode

75. Comments on Timing

76. Architectural Issues

77. SDRAM - Use CAS for Bursts

78. DDR SDRAM
Double Data Rate

79. DRAM Timing

80. RAMBUS DRAM (RDRAM)

81. RDRAM Bandwidth

82. Maximum Bandwidth

83. Normal Bus for DRAM DIMMs

84. RDRAM Bus

85. Deep Pipelining - High Latency

86. RDRAM Addressing

87. Row Activate Command

88. RDRAM System Arch

89. RDRAM Internal Arch

90. Regular DRAM

91. Single Bank DRAM

92. Multi-Bank DRAM

93. Peak Bandwidth

94. ROM

95. ROM

96. ROM

97. ROM

98. ROM Layout

99. ROM Layout

100. Precharged ROM

101. Precharged ROM

102. Other Memory Cells

103. Non-Volatile ROM EPROM EEPROM Flash EEPROM
Erasable Programmable ROM
EEPROM
Electrically Erasable Programmable ROM
Flash EEPROM
Electrically Erasable Programmable ROM that is erased in large chunks
All these devices rely on trapping charge on a floating gate

104. EPROM

105. Programming EPROM
Higher Vth (around 7v) means that 5v Vgs no longer turns on the transistor
SiO2 is an excellent insulator
Trapped charge can stay for years

106. Erasing an EPROM
Erase by shining UV light through window in the package
UV radiation makes oxide slightly conductive
Erasure is slow - from seconds to minutes depending on UV intensity
Also the erase/program cycles are limited (around 1000), mainly as a result of the UV erasing
But, EPROMs are simple and dense

107. EEPROM Thin oxide allows erasing in-system Fowler-Nordheim Tunneling
Floating Gate
Tunneling Oxide
transistor
Thin oxide allows erasing in-system
Fowler-Nordheim Tunneling

108. EEPROM Two transistors instead of one Bigger and not as dense as EPROM
The second keeps you from removing too much charge during erasure
Bigger and not as dense as EPROM
But, more erase/program cycles
On the order of 105
Eventually you get permanently trapped charge in the SiO2

109. Flash EEPROM Essentially the same as EEPROM
But, large regions erased at once
Means you can monitor the voltages and don’t need the extra access transistor

110. EEPROM
Flash

111. Realistic PROM Devices

112. Content Addressable Mem
Asks the question: Are there are any locations that hold this value?
Used for tag memories in associative caches
Or translation lookaside buffers
Or other pattern matching applications

113. Content Addressable Mem
Add the Match line
Essentially a distributed NOR gate

114. Content Addressable Mem

115. Programmable Logic Array

116. PLA Still useful for random combinational logic
Standard cell ASIC tools may be replacing them
They can generate dense AND-OR circuits

117. Pseudo-Static PLA Circuit

118. Dynamic PLA

119. PLA Layout

120. PLA vs. ROM

121. FPGAs Field Programmable Gate Arrays
Array of P-type and N-type transistors
Sources and drains connected to
Power and ground
Metal
Map gate structures to sea of gates
Less expensive – only modify metal masks