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KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures

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Presentation on theme: "KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures"— Presentation transcript:

1 KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures
Thomas Kissinger KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures

2  Efficient parallel access becomes important
Introduction (1) Data Processing … More and more cores and CPUs ~40 GB/s  Efficient parallel access becomes important 8KB … Buffer … More and more main memory per Server (2TB currently) ~100 MB/s Entire data pool in-memory Reduction of disk-accesses memory-accesses is optimization goal Hard Disk Storage

3 Related Work B-Tree based FAST PALM Unbalanced trees Prefix Tree CTrie
Complex locking schemes Comprehensive balancing tasks  Cache-awareness FAST PALM Unbalanced trees Deterministic path Balanced read/update rate  Memory access-optimized Prefix Tree CTrie KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures

4 KISS-Tree Overview Based on Prefix Tree
Specialized version for 32bit keys Latch-free updates Order-preserving 2-3 memory accesses per key Fastest reported read performance for order-preserving in-memory indexes High update performance Heterogeneous in-memory index structure Combination of direct and indirect addressing Takes advantage of virtual memory management of the hardware and the operating system Compression mechanisms

5 Level 1: Virtual Level Decimal Key: 42 Split key in 3 fragments 16bit ( 𝑓 1 ) 10bit ( 𝑓 2 ) 6bit ( 𝑓 3 ) Calculate corresponding 2nd node address from the first fragment Direct addressing No memory required for level 1 Level 2 … Node Node Node Node Node Node Node Node Requirement for Level 2: All nodes have to be stored sequentially in memory KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures

6 Level 2: on-demand level
Change over to indirect addressing 1024 buckets per node containing a compact pointer to the 3rd level node 256 MB maximum Decimal Key: 42 16bit ( 𝑓 1 ) 10bit ( 𝑓 2 ) 6bit ( 𝑓 3 ) Virtual Memory Address Level 2 … 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB Memory Management Unit (MMU) Page Directory Hardware OS Physical Memory Address … 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures

7 Thread-Local Memory Management Subsystem
Level 3: compression Decimal Key: 42 16bit ( 𝑓 1 ) 10bit ( 𝑓 2 ) 6bit ( 𝑓 3 ) 42 64 possible node sizes Bitmap indicates which bucket is in use Only existing values are stored Value Value Value Value 64bit Bitmask Values Read-copy-updates  No in-place updates possible (lost updates) Thread-Local Memory Management Subsystem KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures

8 Thread-Local Memory Management Subsystem
Insert Example 1 Decimal Key: 42 Virtual Page Physically allocated Page 16bit ( 𝑓 1 ) 10bit ( 𝑓 2 ) 6bit ( 𝑓 3 ) 2 … … … … … … 1023 23 1023 1023 10bit 5 4 Value Value Value Value 6bit 3 Thread-Local Memory Management Subsystem KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures

9 … … … … … … Batched Reads 42 938 4459 17 Batch Size = 4
Each thread processes multiple read operation at a time  Software pipelining Better cache usage Prefetching of next nodes possible … … … … … … 1023 23 1023 1023 10bit Value Value Value Value 6bit KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures

10 Evaluation Workloads Evaluation Hardware All Hardware Platforms
Uniform key distribution Sequential workload (keys randomly picked from the sequence range) Evaluation Hardware Intel i (SMP, 4 cores with Hyper-Threading) 8 MB LLC 16 GB main memory Ubuntu 11.10 All Hardware Platforms KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures

11 Read Performance Uniform Distribution
Single-threaded CSB+-Tree: ~3Million Ops/s KISS-Tree: 18 Million Ops/s with one thread (64M Keys) Sequence KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures

12 Update Performance Uniform Distribution Sequence
KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures

13 Hardware Platforms KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures

14 Memory Consumption KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures

15 Conclusion Hardware Trends KISS-Tree Outlook
More and more parallel Hardware High capacities of main memory affordable KISS-Tree Prefix Tree based in-memory index structure 2-3 memory access per key Currently only for 32bit keys Outlook Support for larger keys, especially 64bit Allow in-place updates for existing keys Optimizations for NUMA-systems KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures

16 Thomas Kissinger KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures Questions? Feedback? wwwdb.inf.tu-dresden.de/dexter

17 … … … … … Memory Management RCU-Aware Free Lists Thread-Local Memory
1 1 2 2 64 RCU-Aware Free Lists 64 1 … 1 … 2 2 64 64 Thread-Local Memory 1 … 1 … 63 63 64 64 1 … 63 64 Global Memory KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures

18 Scan vs. Index 813 s 23 s >107 <1µs
About 40 GB/s scan performance with in-memory Databases Real-Time Analytics requires low response time 813 s 23 s >107 <1µs  Indexing is still necessary for ordering, grouping, point- and range-queries KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures

19 Update Rate KISS-Tree: Smart Latch-Free In-Memory Indexing on Modern Architectures

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