1. REFERENCE CIRCUITS
A reference circuit is an independent voltage or current or time (frequency) generator which has a high degree of precision and stability.
Output voltage/current/time should be independent of power supply.
Output voltage/current/time should be independent of temperature.
Output voltage/current/time should be independent of processing variations.
Iref
Load
circuit
Reference
Circuit +
Vref -

2. I-V curves of ideal references

3. Types of commonly used references
Voltage dividers - passive and active.
MOS diode reference.
PN junction diode reference.
Gate-source threshold reference circuit.
Base-emitter reference circuit.
Thermo voltage reference circuit
Bandgap reference circuit

4. Typical variations affecting the references
Power supply variation (main concern here)
Load variation (want ro=∞ for I-ref, ro=0 for V-ref)
Temperature variation (main concern also)
Processes variation (use good process and layout)
Interferences and noise (not considered here)

5. Sensitivity Analysis
A systematic way of evaluating robustness with respect to various sources of errors.
Total percentage error in y =
sum { sensitivity_i * pecentage error_i }

6. rather than sensitivity
For temperature variation, typically use fractional temperature coefficient:
TCF =
rather than sensitivity =

7. Voltage references Passive Divider Limited accuracy, ~6-bit, or 2%
Large static power
for small ro
Large area
Power sensitivity = 1
Temp coeff depends on material

8. These can be used as “start up” circuits.
Active Dividers
These can be used as “start up” circuits.

9. PN Junction Voltage References=
If VCC = 10V, R = 10 kW, and IS = 10-15A, then =

10. Taking ∂/∂T and using: VCC − VREF + kT/q ≈ VCC − VREF:
For a diode:
Taking ∂/∂T and using: VCC − VREF + kT/q ≈ VCC − VREF:
TCF≈ =
where VGO = V is the bandgap voltage of silicon.
If VREF = VBE = 0.6V, TCF of R = 1500 ppm,
then TCF of VREF = ppm/oC

11. HW: Calculate
Calculate TCF

12. MOS equivalent of VBE reference:

14. If VDD = 10V, W/L = 10, R = 100kW, then VREF = 1.97V and
= 0.29
If VDD = 5V, W/L = 100, R = 100kW, then VREF = V and =

15. For temperature coefficient
mo = KT-1.5 ; VT = VT0 - aT or VT(T) = VT(To) - a(T-To)

16. Solving for ∂VREF/∂T and computer TC:
The book has one example of using this.

17. Widlar current source
Vgs1-Vgs2-IoutR2=0
IoR2 +rt(Io/b2)-VEB1=0
Rt(Io)=(rt(1/b2 +4R2VEB2)-rt(1/b2))/2R2

18. Peaking current source:
Vgs1-IinR-Vgs2=0
VEB2=VEB1-IinR
Io=b2*VEB2^2= b2*(VEB1 -IinR)^2
Io = b2*( rt(Iin/b1) - IinR)^2
If VD1 is small, M2 is in weak inversion. If Iin is very small, M1 is in weak or moderate inversion.

20. VDD
Iref
Generically:
Xref
Reference
Circuit +
Vref -
Ideally, Xref is independent of PVT.
The reference circuit then takes no input, but generates an output.
It must contain a feedback loop that is self- stabilized to generate Xref.

21. The VGS based voltage reference
Vref is fed back to the gate
Gate voltage is fed forward to the output at Vref
Ro = R||rds||1/gm
Loop gain = - gm*Ro
= - gm/(gm+gds+1/R)
|Loop gain| < 1.

22. Well-posed-ness of feed back loops
Vref u
Feed forward
Feed back v
The feed back system should not contain an algebraic loop with gain = 1.

23. Example: not well-posed system
If M1 and M2 are matched, M3 and M4 are matched, and lambda effect can be ignored, then there is an algebraic loop with loop gain equal to 1.
 Circuit is not well posed. M4 M3 M2 M1

24. To become well-posed: Include the lambda effect
Well defined solution at Vbn = Vbp
Mismatch one of the transistor pairs
M3 and M4 to have different bulk connection
M3 and M4 to have different VT
Source degeneration on M3
With a resistor
With a transistor
Source degeneration on M4
M3 and M4 to have different sizes
Loop gain is either always >1 or always <1

25. Operating points Vref u Feed forward Feed back v
For any given constant values of u and v, the constant values of variables that solve the the feed back relationship are called the operating points, or equilibrium points.
Operating points can be either stable or unstable.

26. Stable operating point
An operating point is stable if all initial values near the operating point lead to convergence to that operating point.
An operating point is unstable if any or some small perturbation near it causes divergence away from that operating point.
A circuit can have multiple operating points, both stable ones and unstable ones.

27. Small gain theorem
If the loop gain evaluated at an operating point is less than one, that operating point is stable.
This is a sufficient condition.
If the loop gain is > 1, the operating point can still be stable.
Local linearization must have all poles in LHP
Small signal loop gain has PM>0 at UGF

28. Example
Suppose there is an operating point at which all transistors are in saturation.
At this operating point, we can obtain gm and gds for all transistors.

32. y=x
VBN
VBN

33. One quick design strategy

35. y x

36. y
We may do similar analysis near the other operating point.
Putting together, we have:
y=x
VBN x
VBN
VDD

37. Multiple operating points
For a simple circuit as the one above, it is possible to have multiple operating points.
In the example, two are stable:
The desired one with x=y=VBN
The one in weaker inversion
The third operating point is unstable.
Need start-up circuit to prevent getting stuck at the undesired stable operating point.

38. VGS based Current reference
MOS version: use VGS to generate a current and then use negative feed back stabilize i in MOS
Start up
Current mirror
VGS

39. Start up circuit consuming no static current

40. Need to add start-up circuit
Add MOSCAPs between VBP and VDD, or between VBN and VSS
NMOS W ratio and R determines current value
Cascode to improve supply sensitivity
Or use a regulated amp
VBN and VBP may be directly used as biasing voltage for non-critical use M4 M3 M2 M1 R

41. HW:
Assume M1~M4 in strong inversion and M2~M3 in saturation. Let M1 have VTn, M4 have VTp, M2 have Vosn and M2 have Vosp. Both M1 and M2 have mn, ln and both M3 and M4 have mp, lp. L1=L2=L3=L4, W2=kW1, W3=W4.
Write down the drain current equations for M1~M4.
Compute the sensitivity of I2 with respect to VDD. (You can set Vos to 0 for simplicity.)
Compute temp co of I2. (You can set ln and lp to 0 for simplicity.) Note: Vosp is temperature dependent, Vosn is both temperature and I2R dependent, and R is also temperature dependent.
Based on 2 and 3, comment on why this is good circuit and how performance can be improved by proper design.
Comment on why the Wilson current source is not good.

42. VDD sensitivity is improved
Show that:
VDD sensitivity is improved
For low voltage, small amp can be very simple Ap An

45. Cascode version
VDD-Vss must be large enough

46. Cascode version for low voltage
1/5(W/L)p
1/5(W/L)N
K(W/L)N

47. Select Iref (may be given)
Sample design steps:
Select Iref (may be given)
Assume all transistors except those arrowed have the same VEB.
VBN = VSS+VTN+VEB;
VBNC = VSS+VTN+VEB*rt(5);
VBP = VDD-|VTP|-VEB;
VBPC = VDD-|VTP|-VEB*rt(5).
At VDDmin, Needs all transistors in saturation.
For PMOS, need VBN < VBPC+|VTP| = VDDmin-VEB*rt(5). VEB < (VDDmin-VSS-VTN)/(1+rt(5)).
For NMOS, need VBP>VBNC-VTN, VDDmin-|VTP|-VEB > VSS+VEB*rt(5).  VEB < (VDDmin-VSS-|VTP|)/(1+rt(5)).
Since |VTP| is typically larger, so choose the second one. VEB ≈< (VDDmin-VSS-|VTP|)/(1+rt(5)).
With given VEB and Iref, all (W/L)’s can be determined.
Choose K and R: Iref*R=VEB – VEB/rt(K), so R = (1-1/rt(K))*VEB/Iref. Choose K so that a) R size is not too large and b) R+1/gmn/rt(K) is quite bit larger than 1/gmn.

48. VEB based current reference
Start up
VEB=VR

49. A cascoded version to increase ro and reduce VDD sensitivity:
Requires start up
Not shown here
VEB reference

50. HW:
Analyze the sensitivity of the output I with respect to VDD and temperature.
Come up with a start up circuit for the circuit on the previous slide, using only active resisters without RB. Note that you need to make sure that at the desired operating point, the connection from the start up circuit should be turned off.

51. A thermal voltage based current reference
I1 = I2,  J1 = nJ2,
but J = Jsexp(VEB/Vt)
 J1/J2 = n =
exp((VEB1─ VEB2)/Vt)
 VEB1─ VEB2 = Vt ln(n)
I = (VEB1─ VEB2)/R
= Vt ln(n)/R  Vt = kT/q

52. A band gap voltage reference
Vout = VEB3 + I*x*R = VEB3 + (kT/q)*xln(n)
Vout/T = VEB3/T + (k/q)*xln(n)
At room temperature, VEB3/T = ─2.2 mV/oC,
k/q = mV/oC.
Hence, choosing appropriate x and n can make
Vout/T=0
When this happens, Vout = 1.26 V

53. Converting to current

54. General principle of temperature independent reference
Generate a negatively PTAT (Proportional To Absolute Temperature) and a positively PTAT voltages and sum them appropriately.

55. A Common way of bandgap reference

56. VBE has negative temp coeff at roughly -2
VBE has negative temp coeff at roughly -2.2 mV/°C at room temperature, called CTAT
Vt = kT/q is PTAT that has a temperature coefficient of mV/°C at room temperature.
Multiply Vt by a constant K and sum it with the VBE to get
VREF = VBE + KVt
If K is right, temperature coefficient can be zero.

57. In general, use VBE + VPTAT

58. How to get Bipolar in CMOS?

59. Layout
P-active is E
N-well is B
P-substrate is C
Tie both n-well and p-substrate to Vss
Issues: this will not pass LVS
Cadence does not know how to simulate

60. Alternative:
Use PMOST VE
Vsub
Vss
Layout:

61. A conventional CMOS bandgap reference for a n-well process

62. VOS represents input offset voltage of the amplifier.
Transistors Q1 and Q2 are assumed to have emitter-base areas of AE1 and AE2, respectively.
If VOS is zero, then the voltage across R1 is given as

64. If a=1, m=1,

65. In practice, the fabricated value of K (which depends on emitter area ratio, current ratio, and resistance ratio) may not satisfy the given equation.
This will lead to Vref value at testing temp to differ from the theoretically given value.
A resistance value (typically R3) can be then trimmed until Vref is at the correct level.
Once this is done, the zero temp co point is set at the testing temperature.

66. Independent of design parameters!!!

67. If T0 =300, and T varies by +- 60oC, then Vref changes by as much as 25mV*0.04 = 1 mV. That correspond:
1mV/1.26/120oC = 6.6 ppm/oC
In real life, you get about 4X error.

69. This provides an un-symmetric tilt to the quadratic curve.
This provides a faster bending down than the quadratic curve.

71. A major source of Bdgp error is incorrect calibration.
Let T0 be the unkown zero temp co temperature, and Ttest be the test temperature.
If Ttest = T0
Else

72. For example, if Vref is trimmed with an error of 18 mV, this will lead to a slope of 18 mV/300oC at 300oC. In terms of ppm, this is about 50 ppm/oC
The actual Vref error due to this trimming error is actually more than this, because the temperature range now is not symmetric about T0.

73. Another source of error:

74. Bandgap reference still varies a little with temp

75. Causes of errors
Vbe2+Vos
Vbe2
Vbe1

77. This is a problem in CMOS only: b small and r large.