1. Simulate Inverter Momentary Cessation
NERC IRPTF Updates
Songzhe Zhu, California ISO
David Piper, Southern California Edison
Ryan Quint, NERC

2. Modeling Objectives Existing inverter based generators
Generic models shall be able to simulate the momentary cessation and match the performance observed in the actual events
Future inverter based generators
Establish inverter performance guidelines
Generic models shall be examined for modeling capability against the inverter design under the performance guidelines

3. Illustration of Momentary Cessation

4. Momentary Cessation Modeling Requirement
Cease active and reactive currents if voltage is below v1 or above v2
Time delay between voltage is back to range [v1, v2] and recovery starts
Ramp rate limit of active current during recovery
Control of reactive current during recovery
Priority between active and reactive current during recovery

5. MC Modeling Capability of Generic RE Models
Recommendation was to use reec_a model to simulate momentary cessation
Meet most of the modeling requirements by carefully setting up VDL1 and VDL2 blocks, voltage_dip and thld2
Does not simulate the reactive current recovery delay
Conversion of existing reec_b model to reec_a is a challenge

6. User-Written Model to Simulate MC
Replaced in-run epcl with the user-written model for better control of model execution sequence, i.e. when the epcl is executed at each time step of integral.
Interact with reec, pv1e and wt4e models to simulate zero current injection during cessation and recovery delay
At the moment Vt_filt < V1 or Vt_filt > V2, set Imax = 0
At the moment V1 <= Vt_filt <= V2, start and recovery delay timer.
When the recovery delay timer has expired and voltage is still within normal range, Imax is restored to the value in the dynamic model.

7. User-Written Model to Simulate MC (Cont.)
Freeze state variables in reec models during recovery delay.
During recovery delay, Iqmax and Iqmin are 0 to achieve zero current injection. S2 and s3 are winding up, which causes numerical distortion when the delay is over. Set all control gains to 0 to prevent this.

8. User-Written Model to Simulate MC (Cont.)
Include a lock-out mechanism in the user-written model.
After a certain number of successive MCs, the inverters are tripped.
The user-written model is invoked in the dyd file:
epcmod "12ST TAP" "1 " : #9 "blockinv_epcmod.p" 8 "vblk" 0 "delay" 0 "rrpwr" 0 "lockout" 0

9. Output of the MC Model Report MC events TIME MODEL TYPE BUS NO
BUS NAME ID
EVENT
EVENT DETAIL V
reec_b
xxxxx
xxx 1
entering block state
voltage outside of range 0.9-2
entering delay state
delay timer is 1 seconds
entering recovery state
unit will fully recover in seconds
entering normal state
voltage inside of range 0.9-2
BUS NO
BUS NAME ID
MC COUNT
xxxxx
xxx 1

10. Simulation Results – Pg of Solar PV