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Computer Architecture
Verilog HDL
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The Verilog Language Originally developed by Gateway Design Automation as a propriety language for logic simulation in 1984 Later put into use as a specification language for logic synthesis Now, one of the two most commonly used languages in digital hardware design (VHDL is the other) Virtually every chip (FPGA, ASIC, etc.) is designed in part using one of these two languages Supports both structural and behavioral modeling styles
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Behavioral Modeling with Continuous Assignments
input/output specification
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Bitwise Operators comments
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Reduction and Other Operators
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Internal Signals internal signal
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Precedence
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Constants
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Hierarchy
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Tristates high impedance
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Bit Swizzling
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Behavioral Modeling with Always Blocks
sensitivity list
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Behavioral Modeling with Always Blocks
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Latches & Counters
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dependent on all inputs
Combinational Logic dependent on all inputs
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Combinational Logic
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Combinational Logic
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Memories
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Nonblocking & Blocking Assignments
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Nonblocking & Blocking Assignments
incorrect!
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Finite State Machines
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Parameterized Modules
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Pitfalls Incorrect Stimulus List
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Pitfalls Missing begin/end Block
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Pitfalls Undefined Outputs
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Pitfalls Incomplete Specification of Cases
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Pitfalls Shorted Outputs
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