1. ELEC 6970: Low Power Design Class Project By: Sachin Dhingra
Effect of Variation of threshold voltage on power consumption, delay and area of a 32x32 bit array Multiplier
ELEC 6970: Low Power Design
Class Project
By: Sachin Dhingra

2. Outline Introduction Design of the multiplier Background Results
Leakage Power
Threshold Voltage
Results
Conclusion
Future Work
12/1/2018
ELEC 6970: Low Power Design

3. Introduction Design and Verification of an array multiplier using VHDL
Reduction of leakage current of the circuit by variation of the threshold voltage (Vt)
Sub-threshold conduction current decreases as the Vt increases
Increase in Vt also leads to higher switching delays
Aim: To reduce the leakage current by varying the threshold voltage of the transistors and observe its effect on the overall power consumption, delay and area
12/1/2018
ELEC 6970: Low Power Design

4. Leakage Power Leakage Power components Sub-threshold Leakage current
Reverse bias p-n junction conduction
Gate induced drain leakage
Drain source punch through (Short channel effects)
Gate tunneling
Carrier diffusion between the source and the drain region of the transistor
Grows exponentially as Vt decreases IG ID
Isub
IPT
IGIDL n+
Ground
VDD R
Where,
Vt – Threshold voltage
I0 – cutoff i.e. Vgs = Vt
n – experimentally derived constant
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ELEC 6970: Low Power Design

5. Vt = Vt0 + γ[(Φs+Vsb)½- Φs½]
Threshold Voltage
Threshold Voltage is given by the expression:
Vt = Vt0 + γ[(Φs+Vsb)½- Φs½]
Where,
Vt0 - Threshold voltage when source is at body potential
γ – Body effect parameter
Function of doping level, permittivity and oxide thickness
Φs – Surface potential
function of thermal voltage and doping level
Vsb – Source to Body voltage
Hence, Threshold Voltage is a function of:
Doping concentration
Thickness of oxide
Source to Body Voltage
12/1/2018
ELEC 6970: Low Power Design

6. Threshold Voltage Increase in Threshold Voltage Vt variation
Reduction of Leakage power due to decrease in Sub-threshold conduction
Increase in gate delay
α ~ 1 for short channel devices
Vt variation
Body bias control
Vt is a function of Vsb
Vt increases as Vsb increases
Change in process parameters
Doping concentration
Oxide thickness
12/1/2018
ELEC 6970: Low Power Design

7. Multiplier Design and AnalysisA0 A1 A2 A3 B3 B2 B1 B0 Y3 Y4 Y5 Y6
Array
The multiplier was designed in VHDL using nested conditional generate statements and port mapping
Synthesis and Critical path analysis was done using Leonardo
TSMC 0.25µm library
Timing and Power analysis was done using ELDO
TSMC 0.18µm library
Critical Path
(using Leonardo)
12/1/2018
ELEC 6970: Low Power Design

8. Cell Area: 7 gates Critical paths 1 x 2:1 MUX (2 gates)
2 x XNOR2 (2 gates)
1 x AND2
Critical paths
A → Cout
B → Cout
Full
adder B A
Carry in
Sum output
Sum input
Carry out
12/1/2018
ELEC 6970: Low Power Design

9. Multiplier 4x4 32x32 Area: 82 gates Critical paths Area: 6995 gates
A0 → Y7
B2 → Y7
A1 → Y7
32x32
Area: 6995 gates
A0 → Y63
B2 → Y63
A1 → Y63 A0 A1 A2 A3 B3 B2 B1 B0 Y3 Y5 Y6 Y7
12/1/2018
ELEC 6970: Low Power Design

10. Vt variation: Cell Vt (NMOS) Vt (PMOS) ∆Vt (V) Leakage power (pW)
Average Power (µW)
Delay (ps)
0.28
-0.29
-0.2
794795
29.52
65.36
0.38
-0.39
-0.1
4772
28.62
69.8
0.43
-0.44
-0.05
1204.1
27.51
72.12
0.48
-0.49
351.62
26.39
74.33
0.58
-0.59
0.1
100.91
25.57
80.07
0.68
-0.69
0.2
86.16
24.34
87.01
0.88
-0.89
0.4
84.3
22.83
106.79
1.08
-1.09
0.6
83.457
21.93
137.02
1.48
-1.49 1
81.74
20.25
253.84
1.68
-1.69
1.2
80.89
19.61
379.88
2.08
-2.09
1.6
79.2
18.54
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ELEC 6970: Low Power Design

11. 12/1/2018
ELEC 6970: Low Power Design

12. Optimum Value ~ +0.2
The optimal threshold voltage for the cell design which gives the best tradeoff between Leakage Power and Delay is approximately:
+0.7V for NMOS & -0.7V for PMOS
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ELEC 6970: Low Power Design

13. Conclusion
The Leakage Power reduced as the threshold voltage was increased
The Delay of the cell also increased as we incremented Vt
Area of the circuit remained unaffected
Power – Delay product was evaluated to find the optimum value of Vt for the given cell design
∆Vt ~ 0.2 V
Leakage Power reduction = 75%
Delay increase = 17%
Total Power reduction = 8%
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ELEC 6970: Low Power Design

14. Future Work New Library design required
Variation of threshold using Body bias Voltage
New Library design required
Results for Multipliers of different sizes
Extrapolation of results for larger multipliers
Dual threshold design
Threshold assignment algorithm
Analysis of Delay and Power
Analysis of Power and Delay for different design libraries
TSMC 0.18 µm
TSMC 0.13 µm
Detailed study of power estimation and timing analysis tools
12/1/2018
ELEC 6970: Low Power Design