1. Day 17: October 15, 2012 Energy and Power Basics
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 17: October 15, 2012
Energy and Power Basics
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2. Previously Where capacitance arises What drives delay
How to optimize
Power as a limiting constraint
Energy, Power Density
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3. Today Power Sources Static Capacitive Switching Short Circuit (Day 18)
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4. Power
P=I×V
Where should we look at I?
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5. Power P=IV What’s V? What is I? Steady-State (input fixed)?
When input switches
01
10
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6. Observe I changes over time Data dependent At least two components
Istatic – no switch
Iswitch – when switch
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7. Static Power Where does Istatic come from? Subthreshold leakage
Gate-Drain leakage
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8. Data Dependent? How does value of input impact Istatic?
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9. Data Dependent? How does value of input impact Istatic?
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10. Billion Transistor Leakage
4 Billion transistors
Say 1 Billion gates
Each with one W=2 transistor leaking
How much leakage current?
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11. ITRS 2009 45nm Ileak0 = 0.045mm × Isd,leak High Performance Isd,leak
100nA/mm
Isd,sat
1200 mA/mm
Cg,total
1fF/mm
Vth
285mV
Ileak0 = 0.045mm × Isd,leak
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12. Leakage Power 4 Billion Transistor chip doing nothing Total Leakage?
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13. Reduce Leakage? P=VI How do we reduce leakage?
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14. ITRS 2009 45nm Ileak0 = 0.045mm × Isd,leak High Performance Low Power
100nA/mm
50pA/mm
Isd,sat
1200 mA/mm
560mA/mm
Cg,total
1fF/mm
0.91fF/mm
Vth
285mV
585mV
Ileak0 = 0.045mm × Isd,leak
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15. Low Power Process 4 Billion Transistor chip doing nothing
Total Leakage?
Leakage Power?
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16. Switching
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17. Switching Where does current go during switching?
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18. Switching Currents Charge (discharge) output If both transistor on:
Current path from Vdd to Gnd
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19. Switching Currents Iswitch(t) = Isc(t) + Idyn(t)
I(t) = Istatic(t)+Iswitch(t)
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20. Charging Idyn(t) – why changing? Ids = f(Vds,Vgs)
and Vgs, Vds changing
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21. Look at Energy
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22. Energy to Switch
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23. Integrating
Do we know what this is?
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24. Capacitor Charge Do we know what this is? What is Q?
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25. Capacitor Charge
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26. Capacitor Charging Energy
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27. Switching Power Every time switch 01 pay:
E = CV2
Pdyn = (# 01 trans) × CV2 / time
# 01 trans = ½ # of transitions
Pdyn = (# trans) × ½CV2 / time
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28. Charging Power Pdyn = (# trans) × ½CV2 / time
Often like to think about switching frequency
Useful to consider per clock cycle
Frequency f = 1/clock-period
Pdyn = (#trans/clock) ½CV2 f
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29. Charging Power Pdyn = (#trans/clock) ½CV2 f Let a = activity factor
a = average #tran/clock
Pdyn = a½CV2 f
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30. ITRS 2009 45nm C0 = 0.045mm × Cg,total C0 = 0.045 × 10-15 F
High Performance
Low Power
Isd,leak
100nA/mm
50pA/mm
Isd,sat
1200 mA/mm
560mA/mm
Cg,total
1fF/mm
0.91fF/mm
Vth
285mV
585mV
C0 = 0.045mm × Cg,total
C0 = × F
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31. Switching Power 4 Billion Transistors Cload = 22C0 a=0.2 f=1GHz Power?
Organized into 1 billion gates (e.g. nand2)
Cload = 22C0
a=0.2
f=1GHz
Power?
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32. Switching Power V=1V Cload=22C0 ≈ 1 fF = 10-15F P=a(0.5×10-15)(Ngate)f
P=10-16(Ngate)f
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33. Dynamic vs. Static Power
At what speed (f) does leakage power dominate switching power?
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34. Compare WN = 2  Ileak = 9×10-9 A P=a(0.5×10-15) f + 9×10-9 W a=0.2
P=10-16×f + 9×10-9 W
For what freqs does leakage power dominate switching power?
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35. Charging Power Pswitch = a(½C)V2f What values can a take on? a>1?
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36. Data Dependent Activity
Consider an 8b counter
What is activity, a, for:
Low bit?
High bit?
Average across all 8 output bits?
Assuming random inputs (no glitching)
Activity at output of nand4?
Activity at output of xor4?
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37. Glitches Inputs Transition from 0 1 0  1 1 1
What does output look like?
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38. Admin Andre out on Tuesday Back on Wednesday HW5 due Thursday
No office hours
Back on Wednesday
HW5 due Thursday
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39. Ideas Three components of power Ptot = Pstatic + Psc + Pdyn Static
Short-circuit
Charging
Ptot = Pstatic + Psc + Pdyn
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