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Chapter 1 Interconnect Extraction

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1 Chapter 1 Interconnect Extraction
Prof. Lei He Electrical Engineering Department University of California, Los Angeles URL: eda.ee.ucla.edu

2 Outline Capacitance Extraction Introduction Table based method Formula based method Inductance Extraction RLC circuit model generation Reading assignment Finite element method (FEM) based Extraction Overview of FEM FEM based Extraction Flow Homework

3 Capacitance - Introduction
What’s Capacitance? Simplest model: parallel-plate capacitor It has two parallel plates and homogeneous dielectric between them The capacitance is  permittivity of dielectric A area of plate d distance between plates The capacitance is the capacity to store charge charge at each plate is one is positive, the other is negative +Q -Q ++ ++

4 Capacitance - Introduction
For multiple conductors of any shapes and materials, and in any dielectric, there is a capacitance between any two conductors (coupling capacitance). Mutual capacitance between m1 and m2 is C12 = q1/v2 q1 is the charge of m1 v1 =0 and v3 = 0 m1 m3 m2 c23 c13 c12

5 Capacitance - Introduction
How to represent Capacitance? Capacitance is often represented by a symmetric matrix is the self-capacitance for a conductor e.g., c11 =c12+c13 The charge is given by e.g., m1 m3 m2 c23 c13 c12 C = -c21 c22 -c23 -c31 -c32 c33 c11 -c12 -c13

6 Capacitance - Introduction
How to calculate Capacitance? Self-capacitance is sum of total coupling/mutual cap, i.e. To the first order, capacitance exists only between adjacent wires or crossing wires, and can be pre-computed for a set of (localized) interconnect structures Table based Cap. Extraction Formula based Cap. Extraction Cx

7 Capacitance – table/library based method
Table based Cap. Extraction (2.5D method) has two steps: Table (Capacitance coefficients) generation One-time use of 3-D method Capacitance computation Table lookup with linear interpolation and extrapolation Reference: [He-et al, DAC’97]

8 layer i Table generation w s s
1. Lateral, Area and Fringe Capacitances Functions of (w,s) Pre-computed for per-side per unit-length layer i w s s

9 Table generation (cont.)
2. Crossing Capacitances Function of (w,s,wc,sc) w s sc wc layer i

10 Table generation (cont.)
2. Crossing Capacitances s s sc wc wc sc sc w w Ci,i Per-corner Cover(w,s,wc,sc) = 4

11 victim Illustration of Capacitance Computation
Compute the lumped cap for victim

12 Find Nearest Neighbors on Same Layer
victim

13 Add in Per-Side Area, Fringe and Lateral Capacitances
victim w S1 L1 Per-side area capacitance = CA(w,s1) * L1 Per-side fringe capacitance = CF(w,s1) * L1 Per-side lateral capacitance = CL(w,s1) * L1

14 Add in Per-Side Area, Fringe and Lateral Capacitances
victim

15 Find All Crossovers and Crossunders
victim

16 Add in Crossing Capacitances Corner-by-Corner
victim S1 wc sc w One-corner crossover correction = Cover(w,S1,wc,sc)

17 Add in Crossing Capacitances Corner-by-Corner
victim S1 wc w One-corner crossover correction = Cover(w,S1,wc,)

18 Add in Crossing Capacitances Corner-by-Corner
victim S1 wc w One-corner crossover correction = Cover(w,,wc,)

19 Add in Crossing Capacitances Corner-by-Corner
victim wc sc w One-corner crossover correction = Cover(w,,wc,sc)

20 Summary of Capacitance Computation
Find nearest neighbors on the same layer. Add in per-side lateral, area and fringe capacitance w.r.t. each neighbor. Find all crossovers and crossunders. Add in crossing capacitances corner-by-corner w.r.t. each crossover and crossunder. Sum of capacitance components in above steps is the lumped capacitance of the victim.

21 Capacitance – formula based method
Extract the Capacitance with analytical Formulae Formula based on Horizontal and Vertical Parameters Single Line Parallel Lines References: [Sakurai-Tamaru,ED’83][Wu-Wong-et al, ISCAS’96]

22 Capacitance – formula based method
Single Line Example: Unit-length capacitance: Error less than 6% when [Sakurai-Tamaru, ED’83] w Fp Ff t h

23 Capacitance – formula based method
Single Line of Length L Line of length L [Sakurai-Tamaru, ED’83] w t h

24 Capacitance – formula based method
Two Parallel Lines on Same Layer Unit-length capacitance: Error less than 10% when [Sakurai-Tamaru, ED’83] w s t h

25 Capacitance – formula based method
Three Parallel Lines on Same Layer Unit-length capacitance: Recall [Wu-Wong-et al, ISCAS96] w s t h [Sakurai-Tamaru, ED’83]

26 Capacitance – formula based method
Three Parallel Lines within Two Grounds Two Grounds: where One Ground: [Wu-Wong-et al, ISCAS96] w s t h1

27 Reading Assignment [1] J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali and S. H.-C. Yen, "Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology", ACM/IEEE Design Automation Conference, June 1997, pp [2] T.Sakurai, K.Tamaru, "Simple Formulas for Two- and Three-Dimensional Capacitances," IEEE Trans. Electron Devices ED-30 pp (Feb. 1983)

28 Outline Capacitance Extraction Introduction Table based method Formula based method Reading assignment Inductance Extraction RLC circuit model generation Inductance screening Finite element method (FEM) based Extraction Overview of FEM FEM based Extraction Flow Homework

29 Inductance - Introduction
Is RC Model Sufficient? As the clock frequency grows fast, the interconnect impedance is more than resistance Z = R + jωL Inductance should be considered When ωL becomes comparable to R as we move towards GHZ designs and   1/tr Example: wide clock trees Skews are different under RLC and RC models Neighboring signals are disturbed due to large clock di/dt noise

30 Resistance vs Inductance
Length = 2000, Width = 0.8 Thickness = 2.0, Space = 0.8 R and L for a single wire Ls and Lx for two parallel wires

31 Inductance - Introduction
Impact of Inductance 6000u 5u 10u 5u Gnd Clk Gnd RC model RLC model

32 Loop inductance is defined as the induced magnetic flux in the loop
by the unit current in other loop The average magnetic flux can be calculated by magnetic vector potential Aij Ij Loop i Loop j where, represents the magnetic flux in loop i due to a current Ij in loop j where, ai represents a cross section of loop i

33 Loop Inductance (cont.)
The magnetic vector potential A, defined as an integral form So, loop inductance is

34 Problems of loop inductance
Partial Inductance 1 2 3 4 5 Problems of loop inductance The loops (called return paths) are hardly defined explicitly in VLSI In most cases, the return paths are multiple Partial inductance proposed by A. Ruehli The return path is assumed at infinite for each conductor segment It can be directly appliable to circuit simulator like SPICE

35 Partial Inductance (cont.)
Loop inductance between loop i and j is (assume loop i consists of K segments and loop j does M segments) So, loop inductance is

36 Partial Inductance (cont.)
Definition of partial inductance The sign of partial inductance is not considered So, partial inductance is solely dependent of conductor geometry Sign rule for partial inductance where, Skm = +1 or –1 The sign depends on the direction of current flow in the conductors

37 Outline Capacitance Extraction Introduction Table based method Formula based method Reading assignment Inductance Extraction RLC circuit model generation Finite element method (FEM) based Extraction Overview of FEM FEM based Extraction Flow Homework

38 Inductance Extraction from Geometries
Numerical method based on Maxwell’s equations Accurate, but way too slow for iterative physical design and verification Efficient yet accurate models Coplanar bus structure [He-Chang-Shen-et al, CICC’99] Strip-lines and micro-strip bus lines [Chang-Shen-He-et al, DATE’2K] Used in HP for state-of-the-art CPU design

39 Loop Inductance for N Traces
TwL Tw Tw Assume edge traces are AC-grounded leads to 3x3 loop inductance matrix Inductance has a long range effect non-negligible coupling between t1 and t3, even with t2 between them Tw TwR Ts Ts TsL TsR tL t1 t2 t3 tR It is not sufficient to consider only a single net

40 Table in Brute-Force Way is Expensive
TwL Tw Tw Tw TwR TsL Ts Ts TsR tL t1 t2 t3 tR Self inductance has nine dimensions: (n, length, location,TwL,TsL,Tw,Ts,TwR,TsR) Mutual inductance has ten dimensions: (n, length, location1, location2,TwL,TsL,Tw,Ts,TwR,TsR) Length is needed because inductance is not linearly scalable

41 Partial Inductance for N Traces
TwL Tw Tw Tw TwR TsL Ts Ts TsR tL t1 t2 t3 tR Treat edge traces same as inner traces lead to 5x5 partial inductance table Partial inductance model is more accurate compared to loop inductance model Without pre-setting current return loop

42 Propose and validate five foundations
Foundation I: The self inductance under the PEEC model for a trace depends only on the trace itself (w/ skin effect for a given frequency). 6.50 TwL Tw Tw Tw TwR Ts Ts TsL TsR tL t1 t2 t3 tR

43 Inductance – Table based method
Foundation II: The mutual inductance under the PEEC model for two traces depends only on the traces themselves (w/ skin effect for given frequency). 4.66 6.50 6.17 TwL Tw Tw Tw TwR Ts Ts TsL TsR tL t1 t2 t3 tR

44 Inductance – Table based method
Foundation III: The self loop inductance for a trace on top of a ground plane depends only on the trace itself (its length, width, and thickness) TwL Tw Tw Tw TwR TsL Ts Ts TsR tL t1 t2 t3 tR 4.8 tR

45 Inductance – Table based method
Foundation IV: The mutual loop inductance for two traces on top of a ground plane depends only on the two traces themselves (their lengths, widths, and thickness) TwL Tw Tw Tw TwR Ts Ts TsL TsR tL t1 t2 t3 tR 4.8 0.14 tL tR 0.14 4.8

46 Validation and Implication of Foundations
Foundations I and II can be validated theoretically Foundations III and IV were verified experimentally Problem size of inductance extraction can be greatly reduced w/o loss of accuracy Solve 1-trace problem for self inductance Reduce 9-D table to 2-D table Solve 2-trace problem for mutual inductance Reduce 10-D table to 3-D table

47 Outline Capacitance Extraction Introduction Table based method Formula based method Reading assignment Inductance Extraction RLC circuit model generation Finite element method (FEM) based Extraction Overview of FEM FEM based Extraction Flow Homework

48 Inductance – formula based method
Inductance Extraction from Geometries Conductor Geometry Inductance Formulae Self Inductance : Grover(1962), Hoer(1965), Ruehli(1972), FastHenry(1994) Mutual Inductance : Grover(1962), Hoer(FastHenry)(1965), Ruehli(1972) x z Dx Dy Dz y Conductor 1 Conductor 2 T W l (a) Single Conductor (b) Two Parallel Conductors

49 Self Inductance – Grover’s formula
For single straight wire: length: l width: W thickness: T With the filament approximation (W, T<< l), the self-inductance Lself-L can be written as μ is the permeability of conductor. T W l 49

50 Mutual Inductance – Grover’s Formula
For two parallel and aligned wires of the same width W, thickness T, length l, and center-to-center distance D. With the filament approximation (W, T<< l), the mutual-inductance Lmutual-L can be written as Conductor 1 Conductor 2 T W l D 50

51 Extension from Aligned Filaments to Random Ones [Xu-HE, GLSVLSI’01]
Mutual inductance Lab = + - Mutual inductance Lm1 Lm2 Lm3 Lm4 a b

52 Self Inductance – Ruehli’s Formula
where If T/W < 0.01

53 Self Inductance – used by FastHenry
where

54 Comparisons of Self Inductance Formulae
Short Conductor (l/W < 10) Medium Conductor (10 < l/W < 1000) Long Conductor (l/W > 1000) FastHenry O Ruehli X Grover

55 Mutual Inductance – Ruehli’s formula
where x z Dx Dy Dz y Conductor 1 Conductor 2

56 Mutual Inductance – Hoer’s Formula
For multiple filaments where

57 Reading Assignment [1] L. He, N. Chang, S. Lin, and O. S. Nakagawa, "An Efficient Inductance Modeling for On-chip Interconnects", IEEE Custom Integrated Circuits Conference, May 1999. [2] Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Lei He, “Clocktree RLC Extraction with Efficient Inductance Modeling”. DATE 2000 [3] M. Xu and L. He, "An efficient model for frequency-based on-chip inductance," IEEE/ACM International Great Lakes Symposium on VLSI, West Lafayette, Indiana, pp , March 2001. [4] F.W. Grover, Inductance Calculation, Dover, NY, 1962. [5] A.E. Ruehli, “ Inductance calculations in a complex integrate circuit environment,” IBM J. Res. Develop., vol. 16, pp , Sept [6] C. Hoer and C. Love, "Exact Inductance Equations for Rectangular Conductors with Applications to More Complicated Geometries," J. Res. Nat. Bureau of Standards--C. Eng. Instrum. 69C, No. 2, (April-June 1965).

58 HW 1 Use FEM (finite element method) to calculate inductance, where formulae are used to calculate inductance for each filament or each pair of filaments Build RC and RLC circuit models Compare waveform with RC and RLC circuit models After we finish the second part of chapter 1, matlab code will be released with details and as a starting point

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