1. Datapath & Control MIPS
Section 5
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2. Microprocessor
Two components:
Datapath
Control Unit
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3. Two Types of Circuits Combinational circuits Sequential circuits
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4. Clocking
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5. MIPS Datapath
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6. MIPS Datapath
add $s1, $s2, $s3
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7. MIPS Datapath
lw $s1, 8( $s2)
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8. MIPS Datapath
sw $s1, 8( $s2)
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9. MIPS Datapath
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10. MIPS Datapath
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11. DP for R-type & Memory Instr.
Figure 5.10
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12. Datapath for Instruction Fetch
Figure 5.6
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13. Datapath for Branches BEQ $s1, $s2, 25 WHY? Figure 5.9
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14. Immediate address is 16 bits
Datapath for Branches
× 4
Immediate address is 16 bits
Figure 5.9
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15. Almost Complete MIPS Datapath
lw, sw, beq, add, sub, and, or, set on less than
Figure 5.11
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16. Control Unit
Designing the control unit.
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17. ALU Control Instruction OP Function Field ALU op LW 35 100011 add SW43
101011
BEQ 4
000100
subtract
ADD
000000 32
100000
SUB 34
100010
AND 36
100100
and OR 37
100101 or
SLT 42
101010
set on less than
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18. ALU Control Instruction ALUOp Funct. Field ALU action ALU select LW 00
xxxxxx
add
0010 SW
BEQ 01
subtract
0110
ADD 10
xx0000
SUB
xx0010
AND
xx0100
and
0000 OR
xx0101 or
0001
SLT
xx1010
set on less than
0111
Do add. Independent of the Function field.
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19. ALU Control Instruction ALUOp Funct. Field ALU action ALU select LW 00
xxxxxx
add
0010 SW
BEQ 01
subtract
0110
ADD 10
xx0000
SUB
xx0010
AND
xx0100
and
0000 OR
xx0101 or
0001
SLT
xx1010
set on less than
0111
Do subtract. Independent of the Function field.
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20. ALU Control Instruction ALUOp Funct. Field ALU action ALU select LW 00
xxxxxx
add
0010 SW
BEQ 01
subtract
0110
ADD 10
xx0000
SUB
xx0010
AND
xx0100
and
0000 OR
xx0101 or
0001
SLT
xx1010
set on less than
0111
Operation dependent on the Function field.
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21. ALU Control Circuit
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22. The Three Instruction Classes
R-type – add, sub, and, or, slt.
I-type – lw, sw, beq. op rs rt rd
shift
funct
31:26
25:21
20:16
15:11
10:6
5:0 op rs rt
address
31:26
25:21
20:16
15:0
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23. The Three Instruction Classes
R-type – add, sub, and, or, slt.
I-type – lw, sw, beq.
Destination op rs rt rd
shift
funct
31:26
25:21
20:16
15:11
10:6
5:0
Registers to read op rs rt
address
31:26
25:21
20:16
15:0
Destination for lw
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24. More Complete Datapath
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25. More Complete Datapath
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26. Control Signals for R-type
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27. Control Signals for R-type
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28. Control Signals for lw
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29. Control Signals for branch
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30. Control Truth Table InstrOp RegDst ALUSrc Mem2Reg RegWr MemRead MemWr
Branch
ALUOp
R-fmt
000000 1 10 lw
100011 00 sw
101011 x
beq
000100 01
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31. Control Circuit
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32. The Third Instruction Class J
J-type – jump. op
address
31:26
25:0
000010
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33. Jump Instruction
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34. Single-Cycle Implementation
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35. Multi-Cycle Implementation
Fetch
Decode and register fetch
Execution, memory address computation or branch completion
Memory access or R-type completion
Memory read completion
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36. Multi-Cycle Implementation
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37. Multi-Cycle Implementation
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38. Finite State Machine (FSM)
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39. Memory reference FSM
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40. R-type FSM
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41. Branch FSM
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42. Jump FSM
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43. Partial MIPS Instructions
OP (6)
rs (5)
rt (5)
rd (5)
shamt (5)
funct (6) LW 35 rs rd
offset SW 43
BEQ 4 rt
ADD 32
SUB 34
AND 36 OR 37
SLT 42
ADDI 8
imm
OUT 63
* All numbers are in decimal.
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