1. Chapter Five The Processor: Datapath and Control

2. Building the Datapath Use multiplexors to stitch them together t 2 4 M3 R g W m d P C S c s l Z D y P C I n s t r u c i o m e y R a d 1 6 3 2 A L U l M x g W S h f

3. Control Selecting the operations to perform (ALU, read/write, etc.)
Controlling the flow of data (multiplexor inputs)
Information comes from the 32 bits of the instruction
Example: add $8, $17, $18 Instruction Format: op rs rt rd shamt funct
ALU's operation based on instruction type and function code

4. Control e.g., what should the ALU do with this instruction
Example: lw $1, 100($2) op rs rt 16 bit offset
ALU control input AND 001 OR 010 add 110 subtract 111 set-on-less-than
Why is the code for subtract 110 and not 011?

5. ALU Operation
For load and store instruction, use ALU add to compute memory address.
For R-type instruction, the operation of ALU will be determined by the funct filed, or the lower 6 bits of the 32-bit instruction.
For branch instructions, use ALU subtraction.

6. Control Must describe hardware to compute 3-bit ALU control input
given instruction type = lw, sw 01 = beq, = arithmetic
function code for arithmetic
An example of multiple level decoding methodology.
ALUOp
computed from instruction type

7. Setting ALU Control

8. Describing control using a truth table

9. Designing the Main Control Unit
Three instruction classes* : R-type, load or store, branch instruction
Datapath with all necessary multiplexors and all control lines identified:
*Limited to the subset of MIPS instructions studied in this chapter.

10. Control Signals
Seven single-bit control lines, one 2-bit ALUOp control signal
Except for PCSrc, the control signal can be set solely based on the opcode field of the instruction.
To generate PCSrc, we need to AND together a signal from the control unit, which we call Branch, with the Zero signal out of the ALU.

11. The Simple Datapath with the Control Unitg D s t A L U S r c I n u i o [ 3 1 2 6 ] 4 5 M x C l d R W a P C I n s t r u c i o m e y R a d [ 3 1 ] 2 6 5 A M g L U O p W B h S h i f t l e f t 2 r e g i s t e r 2 Z e r o A L U A L U r e s u l t A d d r e s s R e a d M d a t a 1 u M I n s t r u c t i o n [ 1 5 1 1 ] x u D a t a x 1 m e m o r y W r i t e d a t a S i g n e x t e n d A L U c o n t r o l

12. Will use 6 bit opcodes to set the nine control signals
Control and Opcode
Will use 6 bit opcodes to set the nine control signals
Figure 5.18 shows the relationship.
Also refer to Figure 5.22 (p. 312)

13. Control The ALU control block
Simple combinational logic (truth tables)
The ALU control block
PLA implementation of the control unit

14. R-type Instruction Execution Phases
Fetch instruction from memory, increase PC e g D s t A L U S r c I n u i o [ 3 1 2 6 ] 4 5 M x C l d R W a P C I n s t r u c i o m e y R a d [ 3 1 ] 2 6 5 A M g L U O p W B h S h i f t l e f t 2 r e g i s t e r 2 Z e r o A L U A L U r e s u l t A d d r e s s R e a d M d a t a 1 u M I n s t r u c t i o n [ 1 5 1 1 ] x u D a t a x 1 m e m o r y W r i t e d a t a S i g n e x t e n d A L U c o n t r o l

15. Phase 2 Read from two registers h R e g D s t A L U S r c I n u i o [3 1 2 6 ] 4 5 M x C l d W a P C I n s t r u c i o m e y R a d [ 3 1 ] 2 6 5 A M g L U O p W B S h i f t l e f t 2 d r e g i s t e r 2 Z e r o A L U A L U r e s u l t A d d r e s s R e a d M d a t a 1 u M I n s t r u c t i o n [ 1 5 1 1 ] x u D a t a x 1 m e m o r y W r i t e d a t a S i g n e x t e n d A L U c o n t r o l

16. Phase 3 ALU operation B r a n c h R e g D s t A L U S I u i o [ 3 1 26 ] 4 5 M x l C d W P C I n s t r u c i o m e y R a d [ 3 1 ] 2 6 5 A M g L U O p W S h i f t l e f t 2 R e a d r e g i s t e r 1 R e a d r e g i s t e r 2 Z e r o A L U A L U R e a d r e s u l t A d d r e s s M d a t a 1 u M I n s t r u c t i o n [ 1 5 1 1 ] x u D a t a x 1 m e m o r y W r i t e d a t a S i g n e x t e n d

17. Phase 4 Write result to register. r a n c h R e g D s t A L U S I u i[ 3 1 2 6 ] 4 5 M x l C f d W P C I n s t r u c i o m e y R a d [ 3 1 ] 2 6 5 A M g L U O p W B R e a d r e g i s t e r 1 R e a d a 1 r e g i s t e r 2 Z e r o R e a d A L U A L U d a t a 2 r e s u l t A d d r e s s R e a d 1 M d a t a M I n s t r u c t i o n [ 1 5 1 1 ] u x u D a t a x 1 m e m o r y W r i t e d a t a S i g n e x t e n d

18. Datapath for Load Instruction

19. Datapath for Branch-Equal Instruction

20. Complete Datapath (Fig. 5-24)

21. Our Simple Control Structure
All of the logic is combinational
We wait for everything to settle down, and the right thing to be done
ALU might not produce right answer right away
we use write signals along with clock to determine when to write
Cycle time determined by length of the longest path

22. Performance of Single Cycle Implementation
Calculate cycle time assuming negligible delays except:
memory (200 ps), ALU and adders (100 ps), register file access (50ps)
look at the example in the last part of Sec 5.4 M e m t o R g a d W r i A L U O p S c D s P C I n u y [ 3 1  ] 2 6 5 4 P C S r c 3 2 I n s t r u c i o [ 1 5  ] R e g W d a S x A L U l Z D m y M 1 A L U A d d r e s u l t S h i f t l e f t 2 1 1 A L U M u M I n s t r u c t i o n [ 1 5  1 1 ] x u x A L U c o n t r o l

23. Where we are headed Single Cycle Problems:
what if we had a more complicated instruction like floating point?
wasteful of area
One Solution:
use a smaller cycle time
have different instructions take different numbers of cycles
a multicycle datapath

24. High-level Diagram

25. Multicycle Approach We will be reusing functional units
ALU used to compute address and to increment PC
Memory used for instruction and data
Introduce new registers in main functional units
IR for storing instruction, MDR for storing data read from memory
A, B registers for storing data read from registers
ALUOut register for storing ALU results
Our control signals will not be determined solely by instruction
We will use a finite state machine for control.

26. Review: finite state machines
a set of states and
next state function (determined by current state and the input)
output function (determined by current state and possibly input)
We’ll use a Moore machine (output based only on current state) N e x t s t a t e N e x t - s t a t e C u r r e n t s t a t e f u n c t i o n C l o c k I n p u t s O u t p u t O u t p u t s f u n c t i o n

27. Review: finite state machines
Example:
Output: NSLite, EWLite
State: NSGreen, EWGreen
Input: NSCar, EWCar B.10.2: State Diagram

28. Multicycle Approach
Break up the instructions into steps, each step takes a cycle
balance the amount of work to be done
restrict each cycle to use only one major functional unit
At the end of a cycle
store values for use in later cycles (easiest thing to do)
introduce additional internal registers
Need more multiplexors since we are sharing functional units (ALU, memory).
Justified since cost of registers and multiplexor is much less than ALU or memory.

29. MIPS Multicycle Datapath
handling basic instructions e x t n d 3 2 1 6 I s r u c i o [ 5 ] g M A L U l Z m y a B O S h i f t l e 2 P C M m o r y D a W d u x 1 R g s 4 I n c [ 5 ] d d r e s s

30. Multicycle Datapath (with control signals)1 ] M u x 4 A L U O p S r c B R e g D s t W i I n o [ 5 d 3 2 6 S h i f t l e 2 M m o R g I r D a d W P C y u x 1 s n c [ 5 I R W r i t e A L U S r c A M A d d r e s s u A x 1 Z e r o A L U A L U A L U O u t r e s u l t B 2 x 3 M e m o r y d a t a A L U r e g i s t e r c o n t r o l

31. Multicycle Datapath (complete)r D M e m R a d W i t o g P C n I A L U O p S c B s u l [ 5 ] 3 1 - 2 6 x J x t e n d 3 2 1 6 I s r u c i o [ 5 ] g A L U l Z M m y a B S h i f t l e 2 P C M u x 1 R g s r W d a I n c o [ 5 ] 4 1 o n [ 2 5 ] 2 6 2 8 S h i f t l e f t 2 P C [ 3 1 - 2 8 ] M A d d r e s s u x M e m o r y 1 M e m D a t a A L U O u t W r i t e M d a t a 1 u 2 x 3

32. Five Execution Steps Instruction Fetch
Instruction Decode and Register Fetch
Execution, Memory Address Computation, or Branch Completion
Memory Access or R-type instruction completion
Write-back step INSTRUCTIONS TAKE FROM CYCLES!

33. Role of Control Signals
Refer to Figure (p.324) for the action caused by the setting of each control signal.
Pay attention to the actions of 2-bit control signals. (more multiplexors since we are sharing ALUs and memory units in multicycle implementation.)

34. Step 1: Instruction Fetch
Use PC to get instruction and put it in the Instruction Register.
Increment the PC by 4 and put the result back in the PC.
Can be described succinctly using RTL "Register-Transfer Language" IR <= Memory[PC]; PC <= PC + 4; * Can we figure out the values of the control signals? For IR = Memory[PC];
Assert MemRead, IRWrite, set IorD to 0 to select PC as the source of the address. For PC <= PC + 4;
Set ALUSrcA to 0 (sending PC to ALU), ALUSrcB to 01 (sending 4 to the ALU) and ALUOp to 00 (to make the ALU add), Set PCWrite since we need to write result back to PC.
The above two processes occur in parallel.
* What is the advantage of updating the PC now?

35. Step 2: Instruction Decode and Register Fetch
Read registers rs and rt in case we need them
Compute the branch address in case the instruction is a branch
RTL: A <= Reg[IR[25-21]]; B <= Reg[IR[20-16]]; ALUOut <= PC + (sign-extend(IR[15-0]) << 2);
We aren't setting any control lines based on the instruction type (we are busy "decoding" it in our control logic)
Control signal settings: Set ALUSrcA to 0 (so that PC is sent to ALU), ALUSrcB to 11 (so that sign-extended and shifted offset field is sent to ALU), ALUOp to 00 (so ALU adds)

36. Step 3 (instruction dependent)
ALU is performing one of three functions, based on instruction type
Memory Reference: ALUOut <= A + sign-extend(IR[15-0]);
Control signal: Set ALUSrcA to 1 (so that first ALU input is register A), ALUSrcB to 10, ALUOp to 00.
R-type: ALUOut <= A op B; Control signal: Set ALUSrcA to 1, ALUSrcB to 00, ALUOp to 10 (fuct field determines the ALU control signal settings.)
Branch: if (A==B) PC <= ALUOut;
Control signal: Set ALUSrcA to 1, ALUSrcB to 00, ALUOp to 01 (subtract). PCCondWrite needs to be asserted to update the PC if Zero output of the ALU is asserted. PCSource set to 01 so that value written into PC will come from ALUOut.

37. Step 3 (cont’d) Jump: PC <= PC[31-28] || (IR[25-0]<<2);
Control signal: PCWrite asserted, PCSource set to 10

38. Step 4 (R-type or memory-access)
Loads and stores access memory MDR <= Memory[ALUOut]; or Memory[ALUOut] <= B;
Control signal: MemRead asserted (for load), MemWrite asserted (for store), IorD set to 1 (memory address come from ALU)
R-type instructions finish Reg[IR[15-11]] <= ALUOut; Control signal: RegDst set to 1, RegWrite asserted, MemtoReg set to 0.

39. Step 5 Memory read completion
Reg[IR[20-16]]<= MDR; Control signal: MemtoReg set to 1, RegWrite asserted, RegDst set to 0.

40. Summary:

41. Implementing the Control
Value of control signals is dependent upon:
what instruction is being executed
which step is being performed
Use the information we accumulated to specify a finite state machine
specify the finite state machine graphically, or
use microprogramming
Implementation can be derived from specification
Example (p.330): CPI in a Multicycle CPU using the SPECINT2000 instruction mix shown in Figure (p.228)

42. High-level View of the FSM Controly a c s i n t u ( F g 5 . 3 8 ) R - p 9 B h 4 J 1 I f / d 7 S
(Figure 5.32)
(Figure 5.33)
(Figure 5.34)
(Figure 5.35)
(Figure 5.36)

43. Instruction Fetch and Decode Portion

44. FSM for Controlling Memory-Reference Instructions
Has 4 states
To state 0 (Fig. 5.32)

45. FSM for R-Type Instructions
Has 2 states
To state 0 (Fig. 5.32)

46. FSM for Branch Instruction
Single state
To state 0 (Fig. 5.32)

47. FSM for Jump Instruction
Single state
To state 0 (Fig. 5.32)

48. Graphical Specification of FSMu c i o n d e / g f h J m p l B a E x M y R - W b k ( O = ' L ) S U S r c B = 1 A L O p R e g D s t W i M m o a d I P C u n f h 1
How many state bits will we need? S t a r t p e ) ' ) y Q ) - t ' B E J ' = ' = p p ( O O ( P C W r i t e S o u c = 1 A L U B O p n d R g D s M m I a 2 6 8 9 ) ( ' O W p L = ' ' S = W p ' ) O ( 3 5 7 4

49. CPI in a Multicycle CPU
Compute the CPI given 22% load, 11% store, 49% R-format, 16% branches, 2% jumps.

50. Finite State Machine for Control
Implementation: a block of combinational logic and a register to hold current state

51. Implementing FSM Control
Appendix C.3
10 states, 4 state bits S3-S0
Also depends on the opcode (6 bits)
Figure C.3.3 shows the logic equations for the control unit.

52. Example

53. Truth table for the four next-state output bits

54. PLA Implementation
If I picked a horizontal or vertical line could you explain it?

55. ROM Implementation ROM = "Read Only Memory"
values of memory locations are fixed ahead of time
A ROM can be used to implement a truth table
if the address is m-bits, we can address 2m entries in the ROM.
our outputs are the bits of data that the address points to m is the "height", and n is the "width" m n

56. ROM Implementation
How many inputs are there? 6 bits for opcode, 4 bits for state = 10 address lines (i.e., 210 = 1024 different addresses)
How many outputs are there? 16 datapath-control outputs, 4 state bits = 20 outputs
ROM is 210 x 20 = 20K bits (and a rather unusual size)
Rather wasteful, since for lots of the entries, the outputs are the same
i.e., opcode is often ignored

57. Truth Table for the 16 Control Outputs

58. ROM vs PLA Break up the table into two parts
4 state bits tell you the 16 outputs, x 16 bits of ROM
10 bits tell you the 4 next state bits, 210 x 4 bits of ROM
Total: 4.3K bits of ROM
PLA is much smaller
can share product terms
only need entries that produce an active output
can take into account don't cares
Size is (#inputs  #product-terms) + (#outputs  #product-terms) For this example = (10x17)+(20x17) = 460 PLA cells
PLA cells usually about the size of a ROM cell (slightly bigger)

59. Another Implementation Style
Complex instructions: the "next state" is often current state + 1 (C.4.1)

60. Details

61. Control Memory

62. Microprogramming
What are the microinstructions?

63. Microinstruction Fields

64. Possible Values

65. Instruction Fetch and Decoding
Fields asserted in the 1st microinstruction:
Fields asserted in the 2nd microinstruction:

66. Memory-Reference Instructions
Four microinstructions:

67. R-Type Instructions Fields asserted in the 1st microinstruction:
Fields asserted in the 2nd microinstruction:

68. Branch

69. Jump

70. Microprogramming A specification methodology
appropriate if hundreds of opcodes, modes, cycles, etc.
signals specified symbolically using microinstructions
What would a microassembler do?

71. The Big Picture I n i t a l r e p s o F d g m M c S q u E x f + h R Oy t e c h n i q u e l o g i c a r r a y m e m o r y