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Last time Reviewed 4 devices in CMOS Transistors: main device

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Presentation on theme: "Last time Reviewed 4 devices in CMOS Transistors: main device"— Presentation transcript:

1 Last time Reviewed 4 devices in CMOS Transistors: main device
Caps, resistors, diodes, transistors Transistors: main device Regions of operation Equations in each region Small signal model, DC Small signal model, HF Key figures: A0=gm/gds, wT=gm/Cgs

2 Goals Use these devices to build useful circuits
Op amps, with components: Simple amplifiers Diff pairs Current mirrors Biasing circuits Data converters References Comparators Switches Resistor/capacitor/current source arrays

3 Starting point Examine what we can do using A single transistor
Or two transistors

4 Simple transistor circuits
Can use any # of ideal current or voltage sources, resisters, and switches Use one or two transistors Examine various ways to place the input and output nodes Examine various connections for high gain high bandwidth high or low output impedance low input referred noise

5 Single transistor configurations
A transistor is a four terminal device Three choices of input node For each input choice, there are two choices for the output node The other two terminals can be at VDD, GND, virtual short (V source), virtual open (I source), input, or output node Most connections are non-operative or duplicates D and S symmetric; B not as useful

6 2 valid input choice and 1 output choice
Connection of other terminals: or Resister

7 Capacitor Gnd or virtual Common source

8 This is D To VDD Source follower

9 N-channel common gate p-channel common gate

10 Diode connections

11 Building realistic circuits from simple connections
flip vertical  Combine  N common source

12 flip left-right  N common source Combine to form differential pair 

13 Vbb flip upside down to get current source load  Vbb Combine to form differential amp

14 Can also use self biasing
and convert to single ended output  Replace virtual gnd by current source

15 two transistor connections
Start with one T connections, and add a second T Many possibilities many useless some obtainable by flip and combine from one T connections some new two T connections Search for ones with special properties in terms of AV, BW, ro, ri, etc

16 First MOST is CS D1 connects to D2: (with appropriate n-p pairing)
-kvo vo vin CS with negative gm at output node CS Push pull CS

17 When Vx = gnd T2 is not useful VDD When Vx = Vin, T2 and T1 are just one T Vo When Vx = -kVo what do we get? Vx

18 VDD Vx=gnd, M2 is I source Vx = vin, ? Vo Vx = ─ vin, ? M1 M2 Vx = vo, capacitor Vx Vx = kvo, negative gds feedback

19 VDD VDD M3 M4 k k vo -vo M1 M2 vin -vin gm1 M5 AV= gm1vin+gds1vo+ gds3vo-kvogm3=0 gds1+gds3-kgm3 gds1+gds3 AV=  when k = gm3 GBW=gm1/Co = GBW of simple CS

20 D1 connects to S2 VDD VDD just a single NMOST Cascode

21 VDD VDD Vo -kVx -kVo Vx Cascode with positive Vx feedback Cascode with positive Vo feedback

22 VDD VDD VDD Vin Vo Vo Vo Effects on GBW? Folded cascode

23 VDD VDD Vx -kVo -Vx Vo Vo folded cascode with positive feedback

24 VDD M2 M1 Vbb Vin CL Rb flip up-down for source M2 M1 Vbb Vin CL M4 M3 Vyy Vxx VDD connecting D1 to S2 cascoding

25 VDD M4 M2 Vbb Vin- CL M8 M6 M3 M1 Vin+ M7 M5 Vyy Vxx M9 flip left-right to get this differential telescopic cascoded amplifier add M9 to change gnd to virtual gnd GBW=gm1/Co

26 M4 M2 Vin- CL M8 M6 M3 M1 Vin+ M7 M5 Vyy M9 VDD Vx Vo How to connect G3 to –Vx, –kVx, or – kVo Same GBW Gain can be very high

27 M4 M2 Vin- CL M8 M6 M3 M1 Vin+ M7 M5 Vyy M9 VDD Vx Vo How to connect G3 to –Vx, –kVx, or – kVo Same GBW Gain can be very high

28 VDD Vin CL Vbb flip up-down for I sources VDD M1 Vin CL M2 Vbb connecting n-D to p-S

29 VDD VDD folded cascode amp Same GBW Vbb Vin+ Vin- CL

30 VDD VDD How to connect for positive feedback? Vbb Vin+ Vin- CL

31 D1 connects to G2, two stages
VDD VDD VDD VDD two stage CS amplifier CS amplifier with a source follower buffer

32 VDD VDD VDD VDD Vx -Vx -vin Can you connect without loading effect?

33 VDD VDD VDD V? Vx Vx Same as above, only T2 is pMOS Connecting S1 to D2 makes ro really small buffer or output stage

34

35 connecting S1 to D2 V? V?

36 ? ? e.g.

37 M1 is common gate: D1 connects to G2
VDD Vin

38 D1 connects to S2 Vin


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