1. Advanced Digital Design
Metastability
A. Steininger Vienna University of Technology

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Outline
What is metastability
Effects and threats
The unavoidability
MTBU estimation
Countermeasures
Trends
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Digital Logic
The output of a digital logic gate always assumes a defined logic level
The undefined („forbidden“) voltage range in between is assumed only
during transition (very shortly)
for undefined input levels (!)
„1“
„0“
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Important Remarks
Specified behavior of a component can be expected only on condition of its environment behaving as specified.
Digital levels are represented by analog voltages. Also the transistors inside the gates are inherently analog elements. We just use a digital abstraction, since the gates are specified for a digital environment.
Once generated, undefined logic levels have the potential to propagate
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Inverter Example
analog transfer characteristics
undefined input level may lead to undefined output level
propagation of undefined level
uout
Inverter-characteristics
uin
BUT: No „generation“ of undefined levels (for defined inputs) here
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Response Time of a FF
Observation: An input transition during the decision window leads to an (unbounded) increase of clock-to-output delay
tclk2out
CLK
off-spec D
tclk2out,nom
tsetup
thold
tclk2data
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7. Faces of Metastability
A data transition during the setup/hold window violates the environment speci-fications. Consequently the output does not behave as specified. Possibilities
delayed but proper transition
may cause timing problems
creeping through undefined range
generates long undefined level
oscillation
generates erroneous transitions
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8. Metastability: Creeping
ue,2 = ua,1
stable (HI)
Inv 1 5 4
metastable
Inv 2 3
stable (LO) 2 1
ue,1 = ua,2 1 2 3 4 5
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Physical Equivalent
normal operation: sufficient impulse rolls ball over hill
problem case: insufficient impulse
Ball may remain on top („metastable“) for unbounded time
A small disturbance causes the ball to fall in either direction
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Why a Setup/Hold Time?
When swiching the latch from „trans-parent“ to „hold“ the feedback path must be already stable.
Otherwise we feed the storage loop with a marginal condition (pulse width, level), thus creating undefined behavior
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11. Metastability: Oscillation
PW<D1+D2
A pulse with length shorter than the roundtrip delay through the inverter loop can circulate
Thus it appears periodically at the output
 „oscillation“ D1 D2
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2 Ways of Triggering MS
Time domain
S/H violation will cause glitch/runt in the feedback loop
Value domain
Marginal input voltage stored even without S/H violation D L FB D
Clk D L
Clk FB L FB
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13. Why voilate Setup/Hold?
in a closed synchronous system no violations will occur
BUT: no system is really closed
non-synchronous interfaces
clock domain boundaries
fault effects (single-event upsets)
off-spec operation (temp, VCC, frequency)
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Asynchronous Inputs
dec. win. T0
clock period Tclk
setup/hold
asynchronous event
probability of setup/hold violation
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15. Multiple Clock Domains
CLK 1 (Ref)
CLK 2
arbitrary „phase“ relation
setup/hold violation inevitable (fundamentally!)
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16. Metastability: Thread
propagation
undefined logic level/timing at input may produce undefined output
„Byzantine“ Interpretation
Thresholds/timing of different inputs are different (type variations)
marginal input level/timing may be interpreted differently
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17. Metastability Propagation
uout
Inverter-characteristics
data X X
uin
clk
Combinational gates as well as the inverters inside the FF map metastable inputs to metastable outputs
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18. Inconsistent Perception
Metastab. A
threshold A X X 1 B
treshold B
The metastable state may be regarded as „1“ by one FF and as „0“ by another
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Metastability Proofs
Formal proofs exist that
no upper bound on the duration of metastable state can be given
metastability can in principle not be avoided („Buridan‘s Principle“)
Fundamental issue
Mapping from a continuous space to a discrete space involves a decision that may take unbounded time (namely in borderline cases)
Runts create such borderline cases
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20. Metastability Avoidance?
Can‘t we avoid metastability in practice, if we
Attach a Schmitt-Trigger at the output ?
Change the input threshold of the successor stage ?
Use a different storage element ?
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Why use the D-Flipflop?
Metastability is not restriced to D-FFs, it is encountered with
SR-latch, JK-Flipflop, Muller C-Gate,…
basic issue:
Even with perfect input level runts may emerge from looped-back outputs under unfavorable timing conditions
Basically all biststable elements can become metastable
max
min
min
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22. Mitigating Metastability
Metastability cannot be eliminated
in practice systems still work because metastability is very improbable
it can be made more or less probable by design techniques
It can be transformed between its different modes
marginal level
excessive delay
oscillation
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23. Quantifying the Risk of MS
„Upset“
metastable output is captured by subsequent FF after tr
Mean Time Between Upset (MTBU)
expected value (statistics!) for interval between two subsequent upsets
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Resolution Time
clk
asyn
syn
normal operation: tclk2out < tr
upset: tclk2out > tr
tclk2out
tcomb
tSU
tres
asyn
syn
comb. logic
clk
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Parameters
Resolution time tres
interval available for output to settle after active clock edge
Flip-Flop parameters tc ,T0
experimentally determined
time constant tc dep. on transit frequ.
T0 from effective width of decision window
Clock period of FF Tclk = 1/fclk
Average rate of change ldat
Avg. rate of transitions at FF data input
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26. Modeling Metastability
How can we derive this equation?
Which model to apply?
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27. Simple Metastability Model
model bistable element by inverter pair
use linear model for inverter, around midpoint of transfer function („balance point“)
consider „homo-genuous“ case, i.e. closed loop u1 u2
uout
Inverter-characteristics
uout = -A*uin
uin
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Introducing Dynamics
1st order approximation of dynamic behavior: RC element
assume symmetry (same A, RC for both inverters) for simplicity
assume symmetric supply (+VCC/-VCC) against GND -A
RC = t u1 u2
RC = t -A
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29. Differential Equations
Basics:
forward path:
backward path:
Laplace:
time-domain solution:
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The Solution
u20-u10 … difference of initial voltages (charges on Cs); zero at balance point
t … RC constant, bandwidth = 1/RC
A … inverter gain at balance point
A/t … gain bandwidth product of inverter
starting from the initial difference u2 rises exponentially with time towards the positive or negative supply voltage
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Plot of u2 over Time
For a given t we can project „forbidden“ input range back to a „forbidden“ range of the initial voltage difference
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32. Forbidden Initial Rangeu0
The forbidden output voltage range relates to a forbidden range of initial difference voltage (i.e. just after sampling). This range becomes exponentially smaller for high resolution time tres and high gain-bandwidth product A/t.
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Aperture Window TAW
How long does it take for the input voltage difference to cross the forbidden range?
Depends on feedback voltage slope
(and probably on input voltage!)
udiff(t), slope S
+u0,border
u0,border
TAW
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Calibrating TAW
TAW depends on u0,border , which in turn depends on tres
for immediate use of the output:
thus
technology parameter
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Hitting the Aperture
with exponentially distributed inter-arrival time of input events (rate ldat) and sampling with period Tclk (i.e. window TAW is repeated) the upset rate can be calculated as
Hence the MTBU becomes
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36. Putting it all together
1/tC
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37. The widely used equation
expected time between upsets (statistical!)
available resolution time
rate of input events
technology parameters
sampling frequency
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38. Provoking Metastability
asynchronous inputs
multiple clock domains
clock divider (uncontrolled delay)
low timing margins
slow technology (gain/BW prod)
supply drop (excessive delay)
Operation under high temperature
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Determination of T0, tC
experimental:
vary tres
observe MTBU
log graph => straight
slope -> tC
offset -> T0
typical values T0 tC 1
fdat = 1MHz fclk = 10MHz
tr-tCO (ns)
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40. Metastability – Trends
Claim: „Metastability is a non-issue in modern technologies“
log MTBU[s]
2002 (XC2VP4)
1996 (XC4005)
BUT: clock rates have increased by a factor of 16 during that period –
and timing margins have shrunk in the same way! 12 6
tres 5
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41. Mitigating Metastability
avoid/minimize non synchronous IFs
leave sufficient timing margins
use fast technology (gain/BW prod)
ensure proper operating conditions (stable power supply, cooling,…)
basic principle of synchronizers:
trade performance for increased timing margins (tres)
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Synchronizer
Example: Cascade of n Input-FFs
asyn
clk
syn
MTBU calculation: same equation as before, but now individual resolution times sum up:
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MTBF of n-Stage Synchr.
Recall the projection of allowed output range to an input range considering the exponen-tial increase during the resolution time:
u0 for FFk is provided by the output of a preceding stage FFk-1 => we make the same projection again:
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44. Assumptions made so far
linear inverter slope (1st order model)
load independent gain
dominating RC const. (1st order model)
full symmetry (RCs, inverter properties, rising/falling slopes,…)
decreasing exp term neglected
homogenuous case (MUX switching and input signal shape neglected)
equally distributed voltage levels
exponentially distributed input events
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45. What about Oscillation?
Can our model be used for oscillatory behavior?
How / Why not?
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A More general MS Model
ideal amplifier
pure delay
slope limiter
gain -A
delay D
time constant RC slope S
GBWP = A/RC determines dynamics (decay of metastable state)
oscillation for D > RC/A
creeping otherwise
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Summary (1)
The synchronous digital abstraction is valid only in a perfect environment.
When confronted with out-of-spec inputs, digital circuit elements may show unexpected behavior.
The design style has to ensure that out-of- spec inputs are not processed.
In the vaule domain, a marginal signal level (or a runt) may propagate and/or lead to „Byzantine“ interpretation.
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Summary (2)
In the time domain, a glitch may propagate, or cause a bistable element to become metastable.
Metastability is unavoidable whenever a mapping from a continuous domain to a discrete domain is performed.
Every realistic digital system suffers metastability (asyn inputs, clock domains).
Metastability may manifest as excessive delay, creeping behavior or oscillation.
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Summary (3)
Synchronizers trade performance for a reduced probability of a metastable upset.
The MTBU due to metastability can be estimated by a dynamic model of the storage loop.
The model and the measurement of the related parameters are based on many simplifying assumptions and suffer from considerable uncertainties.
Metastability is also an issue for modern technologies. It can be best mitigated by large timing margins.
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