1. ENCM515 -- 21K Interrupts Theory and Practice*
07/16/96
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ENCM K Interrupts Theory and Practice
M. R. Smith,
Electrical and Computer Engineering, University of Calgary, Alberta, Canada ucalgary.ca
12/1/2018 *

2. To be tackled today Review Subroutines and Interrupts
Architectural Issues regarding 21K interrupts
Programming issues regarding 21K interrupts
12/1/2018
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3. Subroutines and Interrupts
Very similar in concept
Very different in implementation
Subroutines occur as part of your normal program flow. You tackle a certain task, written as a subroutine, at a certain location in your code.
Time of starting plays no part in the design of a subroutine.
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4. Subroutines are not interrupts!
Subroutines occur when the programmer wants them to occur
Specific location in program code where called
Specific location in code program where will return to
Can prepare for when they will occur so can pass parameters to them
Rules are -- save non-volatile registers
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5. Interrupts are not subroutines
Interrupts occur when the interrupt wants to occur
NO Specific location in program code where called
NO Specific location in program code where will return to
Can’t prepare for when they will occur so can’t pass normal parameters to them -- need to use semaphores and messages instead
Interrupts may not want to stop
Interrupts may want to use volatile registers but subroutines already using them!
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6. From Manual -- 3.6 Interrupts
Interrupts from internal and external conditions -- priority level
An interrupt forces a subroutine (sic) call to a predefined address -- the interrupt vector -- unique
Normal sequencing occurs after RTI
3 external interrupts (IRQ2,1,0) level or edge triggered
Internal -- arithmetic errors etc
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7. Interrupt request is valid if
Not masked
Interrupts globally enable (bit 12 in MODE1 register)
Higher priority request is not pending. Also can’t interrupt itself -- different from 68k
Valid requests invoke a IS sequence that branches to reserved address
Reserved addresses spaced at 8 (sic) instruction intervals
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8. Interrupt response must be fast
68K interrupt -- not too fast to get into
Finish current instruction (8 cycles)
Save next instruction address (12 cycles)
Save status register (4 cycles at least)
Look in “Vector Table” to find the starting address of the ISR routine (8 cycles to fetch)
Fetch the first instruction in ISR
Save registers
Just as slow to get off!
Reverse of above
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9. 21K processes the interrupt as follows
Output the interrupt vector address (to pm address bus?)
Push current PC (return address) on to PC stack
NOT I6/I7 and the “C” stack -- special hardware stack
If external interrupt, timer interrupt or VIRTPT multiprocessor interrupt
push ASTAT and MODE1 register onto the status stack?
Set bit in latch register IRPTL
Set interrupt mask pointer (IMASKP) to reflect interrupt nesting level. The nesting node (NESTM) bit in the MODE1 register determines whether interrupt nesting is permitted.
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10. RTI instruction causes
Return to address at the top of PC stack (hardware)
Pop value off of the PC stack -- hardware
Recover ASTAT and MODE1 if necessary
Clear IRPTL and IMASKP
Don’t do RTI at the end of the RESET vector, do direct jump -- Special case when starting up the processor
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11. Interrupt latency -- pipeline issues
Stage 1 -- synchronization and latching (1 cycle)
Stage 2 -- recognition (1 cycle)
Stage 3 -- branching (2 cycles)
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12. Interrupt, Single Cycle Instruction
EXECUTE
DECODE
FETCH
n-1
nop
nop v
v+1
n-1 IRPTL
->nop
->nop v
v+1
v+2 n
n+1 v
v+1
v+2
occurs recognized
n pushed onto stack
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13. Branches can’t be interrupts
nop
nop
EXECUTE
DECODE
FETCH
n-1 BRA n
n+1
nop
nop v n
n+1 j
j+1 v
v+1
Occurs and is ignored
n+2 pushed on the stack
j pushed onto stack
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14. Other things can’t be interrupted
Branch
First of two cycles needed to perform a program memory and instruction fetch
third to last iteration of a loop
wait states for external memory
etc
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15. 12/1/2018
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16. Clearing the Current Interrupt*
07/16/96
Ignores any interrupt that is already occurring
When interrupt initially occurs IRPTL bit is set
When interrupt is occurring -- IRPTL bit held clear -- solves a big problem and saves external logic to do equivalent
HOWEVER -- you are losing interrupts and “don’t know” (or is there an OVERRUN bit?)
Except when by using JUMP (CI) instruction as part of the ISR routine code
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17. For more information 3.6 -- Interrupts 3.6.1 -- Latency
Interrupt Vector Table
Interrupt Latch Register
Interrupt Priority
Interrupt Masking and Control
Nesting
Status Stack Save
Software Interrupts -- any, specific
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18. Programing a “21K” interrupt
“Pretend it’s a 68K processor”
Need to set up interrupt service routine
Save non-volatile and volatile registers
code
recover registers
Need to tell processor that “this” interrupt hardware operation is connected to (must cause) “that” ISR
Turn “on” the interrupts
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19. What does “21K” interrupt code REALLY look like -- (NOT ‘C’ based)
Example from a program that “just runs” DFT function on startup and nothing else
We need to control interrupts whilst running “C” code in Lab. 4
Example from program (my test version of Lab. 4) that is running various interrupts (SPORT, IRQ etc)
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20. 21K Processor interrupts -- fast
/* Interrupt Vector table */
.SEGMENT/PM isr_tabl;
.EXTERN fftrad2;
/* The loader begins with the interrupts up to and including the low */
NOP;NOP;NOP;NOP; /* Reserved interrupt */
___lib_RSTI: NOP;
jump fftrad2 (db); /* Begin loader */
r0=0x21ad6b59;
DM(WAIT)=r0;
/* Vector for status stack/loop stack overflow or PC stack full: */
___lib_SOVFI: RTI;RTI;RTI;RTI;
/* Vector for high priority timer interrupt: */
___lib_TMZHI: rti;rti;rti;rti;
/* Vectors for external interrupts: */
___lib_VIRPTI: RTI;RTI;RTI;RTI;
___lib_IRQ2I: RTI;RTI;RTI;RTI; \
Need to change for Lab. 4?
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21. “C model” interrupts -- like this
“C” interrupt handler Jumps somewhere and appears to never return!
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22. BIG Problem
The “C” linker pulls in some very special code to make the interrupts happen in the way it wants to.
The “C” interrupt model must be doing something very similar to what we want to do, so “go with the flow”
We COULD modify the “C” linker code to jump directly to our routines -- see next slide
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23. Modifying “C” interrupt behaviour
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24. But is the effect worth while “at the moment” (I. e Lab
But is the effect worth while “at the moment” (I.e Lab. 4) How many hours spent to save “how many cycles” at 40 MHz? Do we need the extra performance?
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25. Start reading the manuals
There are classes of “C” interrupts built into the “C” model
interrupt( int which, function pointer)
Overhead cycles at least -- saves most registers
interruptf( int which, function pointer)
Overhead cycles -- saves some registers
interrupts( int which, function pointer)
Overhead cycles -- saves very few registers
These functions must be allowing the code to behave in the same way we want to make it work -- so go with the flow
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26. 12/1/2018
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27. Part of interrupt() handler “Saves all registers?
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28. Part of interruptf() handler “Saves volatile registers only?”
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29. End of interruptf() handler Recover registers and then RTI
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30. Start of interrupts() handler ????
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31. “C” model Worked out with Matt and Luigi
There is a “dirty great big structure” being used
Each “C” interrupt is controlled by 6 elements -- (r0 = 6 in code on slide 14)
starting address of the interrupt stored
Info on the register saving model to be used
Info on the register recovery model to be used
is the interrupt active or is this interrupt spurious ?
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32. “C model” interrupts -- like this
GLOBAL INTERRUPTS
LOOK UP TABLE ENTRY
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33. In Lab 4 -- Lets just use “interruptf() “ and “pretend”
What does “pretend” mean -- compromise
Write “interrupt” in assembler
Save any non-volatile/volatile registers used (as if “C” was not handling the interrupts for us)
68K -- on stack
21K -- switch to (some) alternate DAG registers (i0, i1, i2, i3, i9, i10) -- save others to the stack
21K -- switch to alternate R registers
Compensate -- make complicated -- two ISRs -- destroy each others registers if not handled correctly
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34. Interrupts on 21K -- designed to be fast
Finish current instruction (1 cycle) (but what about pipeline issues?)
Save next instruction address (hardware)
Save status register????
Alternate set of registers available (sometimes)
Starting address of the ISR routine at fixed location (0 cycles)
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ENCM K interrupts -- theory and practice Copyright

35. Tackled today Review Subroutines and Interrupts
Architectural Issues regarding 21K interrupts
Programming issues regarding 21K interrupts
12/1/2018
ENCM K interrupts -- theory and practice Copyright