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تراشه ها ي منطقي برنامه پذ ير

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Presentation on theme: "تراشه ها ي منطقي برنامه پذ ير"— Presentation transcript:

1 تراشه ها ي منطقي برنامه پذ ير
مرتضي صاحب الزماني

2 تراشه ها ي منطقي برنامه پذ ير
Text Book: [1] Ulrich Heinkel, et al, “The VHDL Reference: A Practical Guide to Computer-Aided Integrated Circuit Design including VHDL-AMS,” Wiley, 2000. [2] Clive Maxfield, “The Design Warrior’s Guide to FPGA,” Elsevier, 2004. [3] Zoran Salcic, Asim Smailagic, “Digital Systems Design and Prototyping Using Field-Programmable Logic and Hardware Description Languages”, 2nd Edition, 2000 References: Datasheets + References given in the slides مرتضي صاحب الزماني

3 تراشه ها ي منطقي برنامه پذ ير
Marking: Homeworks, Quizes, Project, Midterm Exam, Final Exam. Software: ModelSim, EDK, Quartus مرتضي صاحب الزماني

4 مدارهاي ديجيتال S مرتضي صاحب الزماني

5 Full-Custom مرتضي صاحب الزماني

6 Full-Custom مرتضي صاحب الزماني

7 ASIC: Application-Specific Integrated Circuits
Standard Cell: عناصر در رديفها چيده مي شوند. پورتها در بالا و پايين سلولها (تکنولوژي جديد: روي سلولها). Gate Array: آرايه اي از سلولهاي مشابه. مرتضي صاحب الزماني

8 سلولهاي استاندارد Wires Adder MUX NAND مرتضي صاحب الزماني

9 سلولهاي استاندارد مرتضي صاحب الزماني

10 Mixed RAM/ROM Row based Control Logic Row based CPU مرتضي صاحب الزماني

11 Uncommitted Gate Array
مرتضي صاحب الزماني

12 Committed Gate Array مرتضي صاحب الزماني

13 Gate Array MPLD يا MPGA : برنامه ريزي تراشه در زمان ساخت.
FPLD : برنامه ريزي تراشه به صورت الکتريکي توسط کاربر. مرتضي صاحب الزماني

14 مانند Gate Array تشابه: فقط لایه‌های فلز سفارشی می‌شوند
Structured ASIC مانند Gate Array تشابه: فقط لایه‌های فلز سفارشی می‌شوند هزینه ساخت ماسک‌ها خیلی کم مرتضي صاحب الزماني

15 مانند Gate Array تفاوت: گیت‌های خیلی پیچیده: MUX، LUT
Structured ASIC مانند Gate Array تفاوت: گیت‌های خیلی پیچیده: MUX، LUT  بیشتر لایه‌های فلز ساخته شده‌اند هزینه کمتر و سرعت بالاتر و توان مصرفی کمتر مرتضي صاحب الزماني

16 مقايسه S مرتضي صاحب الزماني

17 Programmable Logic Array (PLA)
مرتضي صاحب الزماني

18 PLA مرتضي صاحب الزماني

19 PLA مرتضي صاحب الزماني

20 PAL فقط AND Plane قابل برنامه ريزي. W = ABC + CD
X = ABC + ACD + ACD + BCD Y = ACD + ACD + ABD مرتضي صاحب الزماني

21 Programmable Array Logic (PAL)
براي پياده سازي مدارهاي ترتيبي معمولا در خروجي، FF قرار دارد. PAL 16R8 مرتضي صاحب الزماني

22 PAL 16R8 مرتضي صاحب الزماني

23 PAL 16R8 مرتضي صاحب الزماني

24 Simple PLD (SPLD) (22V10) مرتضي صاحب الزماني

25 22V10 SPLD مرتضي صاحب الزماني

26 SPLD Macrocell مرتضي صاحب الزماني

27 CPLD Interconection Wires مرتضي صاحب الزماني

28 بخشي از CPLD مرتضي صاحب الزماني

29 ساختار FPGA مرتضي صاحب الزماني

30 ساختار FPGA مرتضي صاحب الزماني

31 Logic Cell مرتضي صاحب الزماني

32 LUT مرتضي صاحب الزماني

33 Logic Cell نمونه Spartan Logic Cell مرتضي صاحب الزماني

34 Programmable Switch Matrix (PSM)

35 Programmable Lookup Tables (LUTs) Programmable routing structure
SRAM-Based FPGA Programmable Lookup Tables (LUTs) Programmable routing structure [Entegra]

36 ASIC Hybrid FPGA & ASIC Use reconfigurable fabric to customize an ASIC
Previously: FPGAs have been used to augment ASIC chips in board level Now, they can be used on a single chip ASIC مرتضي صاحب الزماني

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