1. UNIT-V Interrupt structure of 8086. Vector interrupt table.
Interrupt service routines.
Introduction to DOS and BIOS interrupts.
8259 PIC Architecture and interfacing.
cascading of interrupt controller.

2. An interrupt is an external or internal signal that breaks the normal sequence of execution of instructions, diverts its execution to some other program called “Interrupt Service Routine (ISR).
At the end of each instruction cycle the checks to see if any interrupts have been requested .
After executing ISR, the control is transferred back again to the main program which was being executed at the time of interruption.
Nested interrupts.
In 8086, there are two interrupts pins: 1. NMI INTR
NMI :-- Non Maskable Interrupt input pin which means that any interrupt request at NMI input cannot to masked or disabled by any means.
INTR:-- It can be masked using the Interrupt Flag (IF).

3. If more than one type of INTR interrupt occurs at a time, then an external chip called programmable interrupt controller is required to handle them. (eg: 8259 interrupt controller).
There are two types of interrupts
External interrupts
These interrupts are generated by external devices i.e out side the processor (uing NMI, INTR pins). Eg: Keyboard interrupt.
Internal interrupts
It is generated internally by the process circuit or by the execution of an interrupt instruction. Eg: INT instruction, overflow interrupt, divide by zero. At the end of each instruction cycle, the 8086 checks to see if any interrupts have been requested.

4. 8086 Interrupt Vector Table
The first 1Kbyte of memory of 8086 (00000 to 003FF) is set aside as a table for storing the starting addresses of Interrupt Service Procedures (ISP).
Since 4-bytes are required for storing starting addresses of ISPs, the table can hold 256 Interrupt procedures.
The starting address of an ISP is often called the Interrupt Vector or Interrupt Pointer. Therefore the table is referred as Interrupt Vector Table.
In this table, IP value is put in as low word of the vector & CS is put in high vector.

5. Fig 5.1 Interrupt Vector table of 8086

6. Fig 5.2 Block Diagram and Pin Diagram of 8259

7. 8259A Internal Architecture
Interrupt Request Register (IRR):-
The interrupts at IRQ input lines are handled by IRR internally. IRR stores all the interrupts in it, in order to serve them one by one on the priority basis.
In-Service Register (ISR):-
This register stores all the interrupt requests those are being served, i.e ISR keeps a track of the requests being served.
Priority Resolver:-
This unit determines the priorities of the interrupt requests appearing simultaneously.
The highest priority is selected & stored into the corresponding bit during INTA pulse.
IR0 - highest priority
IR7 - lowest priority ; in fixed priority.

8. Interrupt Mask Register (IMR):-
This register stores the bits required to mask the interrupts inputs. IMR operates on IRR at the direction of the Priority Resolver.
Interrupt Control logic:-
This block manages the interrupt and interrupt acknowledge signals to be sent to the CPU for serving one of the 8 interrupt requests.
This also accepts the interrupt acknowledge (INTA) signal from CPU that causes the 8259A to release vector address on to the data bus.

9. Data Bus Buffer:-
This Tri-state bidirectional buffer interfaces internal 8259A bus the microprocessor data bus.
Control words, status & vector information pass through data buffer during read or write operations.
Read/Write Control logic:-
This circuit accepts and decodes commands from the CPU. This block also allows the status of the 8259A to be transferred on to the data bus.

10. Cascade Buffer/Comparator:-
This block stores & compares the IDs of all the 8259As used in the system.
The 3 I/O pins CAS0 – CAS2 are outputs when the 8259A is used as a master.
The same pins used as inputs when it is in the slave mode.
8259A in master mode, sends the ID of the interrupting slave device on these lines. In slave, will send its pre-programmed vector address on the data bus during the next INTA pulse.

11. Interrupt Sequence in an 8086 system
One or more IR lines are raised high that set corresponding IRR bits.
8259A resolves priority and sends an INT signal to CPU.
The CPU acknowledges with INTA pulse.
Upon receiving an INTA signal from the CPU, the highest priority ISR bit is set and the corresponding IRR bit is reset. The 8259A does not drive data bus during this period.

12. 5. The 8086 will initiate a second INTA pulse
5. The 8086 will initiate a second INTA pulse. During this period 8259A releases an 8-bit pointer on to data bus from where it is read by the CPU.
6.This completes the interrupt cycle. The ISR bit is reset at the end of the second INTA pulse if automatic end of interrupt (AEOI) mode is programmed. Otherwise ISR bit remains set until an appropriate EOI command is issued at the end of interrupt subroutine.

13. Command Words of 8259A
The command words of 8259A are classified in two groups
1. Initialization Command Words (ICWs)
2.Operation Command Words (OCWs)
Initialization Command Words (ICWs):-
Before starts functioning, the 8259A must be initialized by writing two to four command words into the respective command word registers. These are called as Initialization Command Words (ICWs).
If A0 =0 and D4=1, the control word is recognized as ICW1.
It contains the control bits for edge/level triggered mode, single/cascade mode, call address interval and whether ICW4 is required or not, etc.
If A0 =1, the control word is recognized as ICW2.
It stores details regarding interrupt vector addresses.

14. IR7 input is assigned the lowest priority
Once ICW1 is loaded, the following initialization procedure is carried out internally.
The edge sense circuit is reset, i.e by default 8259A interrupts are edge sensitive
IMR is cleared
IR7 input is assigned the lowest priority
Slave mode address is set to 7
Special mask mode is cleared and the status read is set to IRR
If IC4 =0, all the functions of ICW4 are set to zero . Master/slave bit in ICW4 is used in the buffered mode only.
ICW1 , ICW are compulsory
ICW3 , ICW are optional.

15. Fig 5.3 Initialization Sequence of 8259

16. Fig 5.4 Initialization Command Word 1 (ICW1) of 8259
A D D D D D D D D0 A7 A6 A5 1
LTIM
ADI
SNGL
IC4
1=ICW4 Needed
0= No ICW4 Needed
A7-A5 of interrupt vector address
MCs 80/85 mode only
Don’t care to 8086
1=Single
0= Cascaded
Call Address Interval
1=Interval of 4 bytes
0= Interval of 8 bytes
ADI=1 for 8086 based system
1=Level triggered
0= Edge triggered
Fig 5.4 Initialization Command Word 1 (ICW1) of 8259

17. Fig 5.5 Initialization Command Word 2 (ICW2) of 8259
A D D D D D D D D0 1
T 7 T6 T5 T4 T3
A10 A9 A8
For 8085 system:
T7-T3 : they are filled by A15-A11 of the Interrupt Vector Address
A10-A8: these bits are same as the respective bits of vector address
For 8086 system:
T7-T3 : Interrupt type
A10-A8: 3 bits are 0, pointing to IR0.
Fig 5.5 Initialization Command Word 2 (ICW2) of 8259

18. Fig 5.6 Initialization Command Word 3 (ICW3) of 8259
a) Master Mode: SP=1, in buffer mode M / S =1 in ICW4
A D D6 D5 D D3 D2 D D0 1 S7 S6 S5 S4 S3 S2 S1 S0
Sn = 1  IRn input has a slave
Sn = 0  IRn input does not have a slave
b) Slave Mode: SP=0, in buffer mode M / S = 0 in ICW4
A D D6 D5 D D3 D2 D D0 1
ID2
ID1
ID0
ID2-ID0  000 to 111 for IR0-IR7 i.e slave1 to slave8
Fig 5.6 Initialization Command Word 3 (ICW3) of 8259

19. Fig 5.7 Initialization Command Word (ICW4) of 8259
A D D D D D D D D0 1
SFNM
BUF
M/S
AEOI
mPM
0= 8085 system operation
1= 8086 system operation
SFNM=1 : Specially Fully
Nested Mode is selected
1= Automatic End of
Interrupt Mode is
selected
1= 8259 is Master
0= 8259 is slave
If BUF=0, M/S is neglected
1= Buffered mode
0= Un buffered mode
Fig 5.7 Initialization Command Word (ICW4) of 8259

20. Operation command words (OCWs)
Once ICW registers (accepting the interrupts) are initialized, 8259 is ready for its normal function.
8259 has its own ways of handling the received interrupts called as modes of operation. These can be selected by programming i.e writing 3 OCW registers.
OCW1: It is for mask the unwanted interrupt requests.
OCW2: It controls the end of interrupt, the rotate mode and their combination
OCW3: It is for set or reset for special mask mode

21. Fig 5.8 Operation Command Word of 8259

22. Operating Modes of 8259 Fully Nested Mode
This is the default mode of operation of 8259A.
End of Interrupt (EOI)
Specific EOI
Determines which ISR bit is to be reset on EOI
2. Non-Specific EOI
Automatically reset the highest ISR bit out of those already set.
Automatic Rotation
This is used in the applications where all the interrupting devices are of equal priority.
Automatic EOI Mode
Till AEOI=1 in ICW4, the 8259A operates in AEOI mode.
In this mode, the 8259 performs a non-specific EOI operation at the trailing edge of the last INTA pulse automatically.

23. Specific Rotation
In this mode a bottom priority level can be selected, using L2,L1, L0 in OCW2 and R=1,SL=1, EOI=0.
If IR5 is selected as a bottom priority , then IR IR IR
Special Mask Mode
When a mask bit is set in OCW, it inhibits further interrupts at that level & enables interrupt from other levels which are not masked.

24. Poll command Edge & Level triggered mode LTIM=0 edge triggered
LTIM=1 level triggered in ICW1
Reading 8259 status
OCW3 is used to read IRR & ISR while OCW1 is used to read IMR. Reading is possible only in no polled mode.
Poll command
In this mode, the INT output is neglected.
The poll mode is entered by setting P=1 in OCW3. The 8259A is polled by using software execution by µp instead of the requests on INT input. It is not used in 8086.

25. Special Fully Nested Mode (SFNM)
This mode is used in more complicated systems, where cascading is used and the priority has to be programmed in the master using ICW4.
In this mode the master interrupts the µp only when the interrupt device has a higher or the same priority than the one currently being served.
Buffered Mode
When the 8259A is used in the systems in which bus driving buffers are used on data buses (e.g. cascade systems) the problem of enabling the buffers arises. The 8259A sends a buffer enable signal on SP / EN pin whenever data is placed on the bus.
Cascade Mode
The master controls the slaves using CAS0-CAS2 which act as chip select inputs for slave. In this mode, the slave INT output are connected with master IR inputs. EOI issued twice one for master other for slave.

26. Fig 5.9 Interfacing with 8086

27. Fig 5.10 Example of Two Cascaded PICs

28. Interfacing and Programming 8259
Problem:
Show 8259A interfacing connections with 8086 at the address 07x. Write an ALP to initialize the 8259A in single level triggered mode, with call address interval of 4, non-buffered, no special fully nested mode. Then set the 8259A to operate with IR6 masked, IR4 as bottom priority level, with special EOI mode. Set special mask mode of 8259A. Read IRR and ISR into registers BH and BL respectively. IR0 of 8259 will have type 80h.

29. ICW1 ( to set single mode, address interval of 4, level triggered
ICW1 ( to set single mode, address interval of 4, level triggered mode, ICW4 is needed)
A0 D7 D6 D5 D4 D3 D2 D1 D0
ICW1 = = 1Fh
2. ICW2 (to select IR0)
A0 D7
ICW2 = = 80h
3. ICW3  Not needed , because 8259 is in single mode.
4. ICW4 (to select system)
A0 D7
ICW4 = = 01h

30. 5. OCW1 (to mask IR6)
A0 D7
OCW1 = = 40h
6. OCW2 (to set Specific EOI with Rotating Priority, IR4 is Bottom priority)
OCW2 = = E4h
7. OCW3 (to set Special Mask Mode, and read IRR, ISR)
a) OCW3 = = 6Ah (to read IRR)
b) OCW3 = = 6Bh (to read ISR)

31. ALP program: ASSUME CS:CODE CODE SEGMENT START: MOV DX, 0070h
MOV AL, IFh ; for ICW1
OUT DX, AL
MOV DX, 0702h ; for ICW2
MOV AL, 80h
MOV AL, 01h ;for ICW4
MOV AL, 40h ; for OCW1

32. MOV AL, 0E4h ; for OCW2
MOV DX,0740
OUT DX, AL
MOV AL, 6Ah ; for OCW3
MOV AL, 6Bh ; for OCW3
IN AL,DX
MOV BH,AL
MOV AH,4Ch ;Return to DOS
INT 21H
CODE ENDS
END START

33. DOS & BIOS Interrupts BIOS Interrupts I. INT 16h :- for Keyboard Input
These interrupts include reading a character from keyboard & getting the status of the keyboard.
Function 10h:- (Read keyboard character)
This standard keyboard operation checks the keyboard buffer for an entered character.
If none is present, it waits for the use to press a key. If a character is present, the ASCII code of the key is returned to AL & its scan code to AH register.

34. Eg:
MOV AH,10h
INT 16h
CMP AL, ‘Y’
JE Enter
The key pressed is not shown on the screen.
Function 11h:- (Determine if character is present)
If the character is present in the keyboard buffer, this operation clears the ZF returns the character to AL & its scan code to AH & character remains in the buffer.
If no character is present, the operation sets the ZF & does not wait for a key like the function 10h.

35. II. INT 10h :- for Video Services
BIOS INT 10h supports many services to facilitate
1.Function 00h :- (Set video mode)
A video made scan be text mode or graphics mode. The generally used video mode is 25 rows X 80 columns, color, text mode .
To set a mode we have to load function code in to AH & mode number into AL.
Ex:
MOV AH,00h ; loading function code
MOV AL, 03h ; standard color text.
INT 10h ; call interrupt service routine.

36. 2. Function 05h :- ( select active page)
Function 05h lets you select the page that is to be displayed in text or graphics made.
We can create new pages & request alternating between pages
Eg:
MOV AH, 05H ; Request active page
MOV AL ,00h ; page 0 is selected
INT 10h

37. 3. Function 02h :- (Set cursor position)
This function is used to set the cursor position anywhere on the screen.
The Row no. & Column no. are given in DH & DL registers & the BH register should contain the page no.
Eg:
MOV AH, 02h ; request to set cursor
MOV BH, 00h ; page 00h
MOV DH, 16 ; Row=16
MOV DL, 32 ; Column=32
INT 10h

38. 4. Function 03h :- ( Return curser status)
This function is used to determine the position of curser & the size of the curser. The page No. has to be mentioned in BH register.
Ex:
MOV AH, 03h ; Request curser location
MOV BH, 00h ; Page No: is 0
INT 10h
Out put : DH: row No.
DL; column No.
CH : Starting Scan time
CL : Ending Scan time.

39. 5. Function 09h : ( Display character & Attribute)
This operation displays specified No. of characters on the screen accordingly to the given attribute.
The character is displayed at the current position of cursor.
AL ASCII character
BL Attribute value
BH Page No.
CX count
Ex: The following code prints ten Ts
MOV AH, 09h ; Request Display
MOV AL, ‘T’ ; T to be displayed
MOV BH, 00h ; page 0
MOV BL, 02 h ; black back-ground & green fore ground
MOV CX , 0A h ; counter ( ie. 10’T’s)
INT 10h

40. DOS Interrupts
INT 21h :-
1. Function 01h :- (keyboard input with Echo)
This is similar to INT 16h’s 10h function but this function displays keyboard & does not return scan mode.
After the interrupt ; we have ASCII code in AL
To get a scan code for this key in AL, we should repeat INT 21h immediately.
Ex:
MOV ah, 01H ; Request keyboard input
INT 21h

41. Function 07h :- (Keyboard input without Echo)
It is like function 01h, except that it doesn’t echo the key onto the display.
This is useful for accepting passwords that are to be invisible.
Eg:
MOV AH, 07h ; request keyboard input
INT 21h
Function 0Bh :- (check keyboard status)
This operation returns FFh in AL if input character is available in the keyboard buffer
00h if no character is available. This doesn’t wait for the user to press the key.

42. Function 02h :- (Screen display)
This is useful for displaying single characters.
DL – character
Ex:
MOV AH, 02h ;request character display
MOV DL, ‘S’
INT 21h
Function 09h :- (Displaying strings)
This function requires the string to be displayed to end with a ‘$’ sign.
String DB “Enter your name: $”
MOV AH, 09h ; request display
LEA DX, String ; load address