1. Multiplier-less Multiplication by Constants
Dr. Shoab A. Khan

2. Multiplication by Constant
In many algorithms a large percentage of multiplications are by constants
Complexity of a general purpose multiplier is not required
Generate Partial Products (PPs) only for 1s in the constant multiplier
The number of PPs can be further reduced using canonic sign digit format

3. Example: FIR Filter In an FIR filter all coefficients are constant
For a fully parallel implementation, general purpose multipliers are not required
Coefficients are converted in canonic sign digit form

4. Canonic Sign Digit (CSD)
No 2 consecutive bits are non-zero
Contains minimum possible number of non-zero bits
Representation is unique

5. CSD is obtained using string property
Canonic Sign Digit (CSD)
CSD is obtained using string property
Examples a Q1.7 format number
= =
→ →
k = –7
Kx = x20 - x x2 –7

6. FIR filter
Convolution summation with constant coefficients h[k]

7. Conversion of FIR Coefficient in CSD
Only one nonzero CSD digit for approximately each 20 dB of stopband attenuation
Four non-zero digits per coefficient for 80 dB stopband attenuation

8. Example: CSD Representation
Let a coefficient is
Converting to CSD and keeping 4 non-zero digits:

9. CSD multiplier 1 s s s 1 s s s s s s s 1 s s s s s s s s s s
xn as it is 1
Shift xn by 3 Take 1’s complement
Add a 1 to the LSB, sign extension
s s s 1
Shift xn by 7 Take 1’s complement,
Add a 1 to the LSB, sign extension
s s s s s s s 1
Shift xn by 10 Take 1’s complement,
Add a 1 to the LSB, sign extension
s s s s s s s s s s

10. CSD Multiplier in 5-coeff FIR filter
REG xn N
Xn-1
Xn-2
Xn-3
Xn-4 h0 h1 h2 h3 h4

11. An Optimal Direct Form FIR Filter Architecture

12. Example: CSD Representation

13. CANONICAL SIGNED DIGIT REPRESENTATION FOR FIR DIGITAL FILTERS
CSD FIR paper
CANONICAL SIGNED DIGIT REPRESENTATION FOR FIR DIGITAL FILTERS

15. Optimized DFG Transformation
Use compression tree and remove the use of CPA in a feedback loop
The result is kept in partial sum and partial carry form
The first order difference equation changes to

16. Example 1: First Order IIR Filter
DFG with one adder and one multiplier in the critical path.
Transformed DFG with Wallace compression tree and CPA outside the feedback loop

17. Example 2: DFT 2nd Order IIR Filter

18. Example: Optimal Mapping: Design Option 1
Optimized implementation with CSD multipliers, compression trees and CPA outside the IIR filter

19. Design Option 2
Using unified reduction trees for the feedforward and feedback computations and CPA outside the filter

20. Design Option 3
CPA outside the feedback loop

21. FIR Filter: Direct Form

22. All multiplications are implemented as one compression tree and a single CPA

23. Example: Conversion to Fixed-Point
h[n] = [ ]
h[n] = round(h[n]*215) =
[ ]
16’b0000_0110_0100_1010
16’b0011_1100_0000_0000
16’b0011_1101_1011_0110

24. Conversion in CSD

25. Keeping maximum of 4 non-zero CSD in each coefficient results in

26. Input to Compression Tree

27. CV Computation for first CSD multiplier

28. Pipelined DF FIR Filter
Pipeline direct form FIR filter for FPGAs with DSP48 blocks

29. Transpose Direct Form FIR Filterxn
Critical Path h0 h1 h2 h3 h4 X X X X X
xnh2
xnh3
xnh4
xnh0
xnh1 + + + +

30. Critical Path

31. Filter Implementation

32. TD FIR with one stage of pipelining registers

33. Deeply pipelined TDF FIR filter with critical path equal to one full adder delay

34. Same Example

35. TDF Implementation

36. Example from the Book

37. Hybrid FIR Filter Structure

38. Hybrid Designs

39. Complexity Reduction
Adv DSD contents

40. Complexity Reduction
Constituent sub graphs that are shared in the original graph
Example: three multipliers, 3, 53 and 585 with x

42. Optimized Implementation
Selected sub-graphs from previous slide

43. Find common sub-expression
Eliminate their re-use

44. Example: Common Sub-expression Elimination

45. Horizontal Common Sub-expressions for the example in the text

46. Vertical Sub-expressions Elimination

47. Common Sub Expression

48. Optimized implementation exploiting vertical common sub-expressions

49. Example of horizontal and vertical sub-expressions elimination

50. Distributed Arithmetic Based Design
Yet another way of looking at dot product design

51. ROM for Distributed Arithmetic
x2b
x1b
x0b
Contents of ROM 1 A0 A1
A1+ A0 A2
A2+ A0
A2+ A1
A2+ A1+ A0

52. DA for computing the dot product of integer numbers for N=4 and K=3

53. Look-up table x2b x1b x0b Contents of ROM 1 A0 3 A1 -1 A1+ A0 2 A2 51 A0 3 A1 -1
A1+ A0 2 A2 5
A2+ A0 8
A2+ A1 4
A2+ A1+ A0 7

54. DA-based architecture for implementing an FIR filter of length L and N-bit data samples

55. Cycle by cycle working of DA
Address
LUT
Accumulator
3’b100 5
000101_000 1
3’b111 7
001001_100 2
3’b000 -1
000011_110 3
3’b101 8
111001_111

56. DA-based parallel implementation of an 18-coefficient FIR filter setting L=3 and M=6

57. A LUT-less implementation of a DA-based FIR filter

58. A parallel implementation for M=K uses a 2:1 MUX, compression tree and a CPA

59. Reducing the output of the multiplexers using a CPA-based adder tree and one accumulator

60. DA-based IIR filter design

61. Two ROM-based design

62. One ROM-based design

63. DFT implementation using circular convolution

64. Optimized TDF implementation of the DF implementation in previous figure

65. Questions/Feedback !!