1. Hardware-Accelerated Signaling
―Design, implementation
and Implications
Good afternoon, thank you all for attending my dissertation defense. The topic of my dissertation is “Hardware-Accelerated Signaling – Design, Implementation and Implications.”
Haobo Wang
November 15, 2004

2. Outline Background and problem statement
OCSP: a performance-oriented signaling protocol and its hardware implementation
A subset of RSVP-TE signaling protocol and its hardware implementation
Comparison of signaling transport options
Implications of hardware-accelerated signaling
Conclusions and future work
Here is the outline of my dissertation.
First is the background and problem statement. My work focuses on the hardware-accelerated implementation of signaling protocols. As a first step, we designed and implemented a signaling protocol called OCSP: Optical Circuit-switching Signaling Protocol. It is a performance-oriented signaling protocol and specifically designed for SONET switches. By saying “performance-oriented”, I mean there are several targets when designing a signaling protocol, such as flexibility, and performance. Our primary concern of designing OCSP is achieving high performance.
There are lots of signaling protocols for different connection-oriented networks, such as
2018/12/2

3. Outline Background and problem statement
OCSP: a performance-oriented signaling protocol and its hardware implementation
A subset of RSVP-TE signaling protocol and its hardware implementation
Comparison of signaling transport options
Implications of hardware-accelerated signaling
Conclusions and future work
2018/12/2

4. Background Signaling protocol
Set up and tear down connections in connection-oriented networks
Control-plane protocol
Signaling protocols are primarily implemented in software
Two reasons: complexity and the requirement for flexibility
Price paid: poor performance
RSVP-TE for GMPLS
Support a wide range of connection-oriented networks
Being implemented by switch vendors
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5. Network and node views
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6. Two questions Question 1: why connection-oriented (CO)?
Inherent support for QoS
Can connectionless networks provide QoS? Yes, but
Over-provisioning -> low utilization
Question 2: What the drawbacks of CO?
Call setup overhead – signaling message propagation delay, processing delays, and transmission delays
Call handling capacities of today’s switches are limited
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7. Problem statement
How to overcome the drawbacks of CO ― Hardware-accelerated signaling?
Determine whether signaling protocols can be implemented in hardware and demonstrate it with an actual implementation
Study how to reduce signaling message trans-mission delays
Explore the impact of hardware-accelerated signaling protocol implementations
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8. Related work How to achieve fast signaling?
New, simplified signaling protocols: YESSIR, PCC
Hardware implementation: FRP (ASIC, not flexible)
A simplified version of RSVP-TE intended for hardware implementation
“Keep It Simple” Signaling – still on the blueprint
Other comparable protocols implemented in hardware
TOE: TCP/IP Offload Engine
TCP switching
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9. Outline Background and problem statement
OCSP: a performance-oriented signaling protocol and its hardware implementation
A subset of RSVP-TE signaling protocol and its hardware implementation
Comparison of signaling transport options
Implications of hardware-accelerated signaling
Conclusions and future work
2018/12/2

10. Optical Circuit-switching signaling Protocol - OCSP
Performance-oriented, optimized for hardware implementation
Specifically designed for SONET switches
Implemented on WILDFORCE FPGA board
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11. Hardware platform of the implementation
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12. Simulation and implementation results for OCSP
Setup
Setup Success
Release
Release Confirm
Clock
cycles
77-101 9 51 10
Assuming a 25 MHz clock
Total setup and teardown time: 5.9 to 6.8 us
Call handling capacity of 150,000 calls/sec
Device
Resource
Eq.Gates
CPE0
XC4036XLA
62%
22,000
PE1
XC4013XLA 8%
1,000
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13. Outline Background and problem statement
OCSP: a performance-oriented signaling protocol and its hardware implementation
A subset of RSVP-TE signaling protocol and its hardware implementation
Comparison of signaling transport options
Implications of hardware-accelerated signaling
Conclusions and future work
2018/12/2

14. Challenges for hardware implementation of RSVP-TE
A large number of messages, objects
Maintaining state information
Many data tables
Support for timers
Global connection reference
Flexible TLV style object……
Can be overcome
by defining a sub-
set of RSVP-TE
Length
Type
Value
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15. Processing of Path message
Incoming Connectivity table
Outgoing Connectivity table
Index
Return
Prev_IP_Addr_User
Prev.I/F ID
In.I/F ID 1 5
Index
Return
Next_IP_Addr_User
Seq.#
Out.I/F ID 1 3 IP IP IP IP IP
Int.#5
Int.#3
Int.#10
Int.#1
Routing table
Outgoing CAC table
Index
Return
Dest_IP_Addr.
Next_Hop_Addr_User
Index1
Return
Out.I/F ID
Avail. BW. 3
State table
User/Control Mapping table
Index
Return
Global Conn Ref
Ctrl plane info.
User plane info
Traffic
State …
Index
Return
Next_IP_Addr_User
Next_IP_Addr_Ctrl
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16. Architecture of the hardware signaling accelerator (FPGA)
Message parsing
Message processing
Message assembling
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17. Functional modules of the hardware signaling accelerator
Incoming message buffer
Two-level message buffering and FIFO interface
Object dispatcher
Two-level dispatching and distributed decoding – TLV challenge
Data table management
Table access arbiter and TCAM/SRAM interfaces
Resource management
Hierarchical resource allocator and CAC table
Retransmission management
Retransmission buffers, timers, exponential back-off
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18. Architecture of the prototype board
Message Buffer
SRAM
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19. Main on-board modules Hardware signaling accelerator: FPGA
957-pin BGA, 6 separate clock signals, 3 I/O levels
High-speed (100MHz)
1Gbps signaling channel: GbE MAC+SerDes+ optical transceiver
Demonstrate 250,000 calls/sec call handling rate
High-speed interface: 125MHz
Incoming message buffer: FIFO
Hardware/software interface
Data tables: TCAM and SRAM
User plane device: switch fabric
High-speed LVDS signals
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20. Organization of the data tables
Routing table
CAC table
Incoming Conn tbl
Outgoing Conn tbl
User/Ctrl
Mapping tbl
State table
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21. Clock and power distribution schemes
Clock distribution scheme
Power distribution scheme
Two extra power supplies
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22. Processing of signaling message — simulation results
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23. Implementation and simulation results
Implementation results
Device
PCI core
Resource
Eq.Gates
Max freq.
XC2V3000
w/o PCI
12%
360,000
90MHz
w/ PCI
21%
630,000
50MHz
Simulation results
Path
Resv
PathTear/ResvTear
Clock cycles 40 32 19
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24. Outline Background and problem statement
OCSP: a performance-oriented signaling protocol and its hardware implementation
A subset of RSVP-TE signaling protocol and its hardware implementation
Comparison of signaling transport options
Implications of hardware-accelerated signaling
Conclusions and future work
2018/12/2

25. In-band signaling and out-of-band signaling
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26. Models for in-band signaling and out-of-band signaling
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27. Set-up delay analysis
Total delay = processing delay + network delay + transmission delay (retransmissions)
Assuming T0 = 3Tn, M/D/1 queue for E[Ttx], we have
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28. Numerical results
In-band/out-of-band signaling with software signaling, wide area
In-band/out-of-band signaling with software signaling, metro area
In-band/out-of-band signaling with hardware signaling, wide area, μtx<<μproc
In-band/out-of-band signaling with hardware signaling, wide area, μtx=μproc
In-band/out-of-band signaling with hardware signaling, metro area, μtx<<μproc
In-band/out-of-band signaling with hardware signaling, metro area, μtx=μproc
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29. A sum-up of the comparison
With hardware signaling accelerators
In-band signaling is the way to go
Network delays dominate the total delay
With software signaling processors
In wide area –> in-band signaling
In metro area –> out-of-band signaling is a good choice
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30. Outline Background and problem statement
OCSP: a performance-oriented signaling protocol and its hardware implementation
A subset of RSVP-TE signaling protocol and its hardware implementation
Comparison of signaling transport options
Implications of hardware-accelerated signaling
Conclusions and future work
2018/12/2

31. End-to-end circuits for large file transfers
End-to-end circuits only justifiable for large files
Define a crossover file size , per-circuit utilization is given by
Assuming 10Mbps signaling link, 100Mbps data link, 20 switches, in order to achieve 90% per-circuit utilization
Crossover file size
HW sig. (4us)
SW sig. (200ms)
Metro area (0.1ms)
40KB
80MB
Wide area (50ms)
330KB
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32. Fractional offered load
Assuming file size follows pareto distribution
Define fractional offered load
% of
40KB
81%
330KB
71%
80MB
51%
With hardware-accelerated signaling
In metro area, 81% of the offered load can be transferred through end-to-end circuits
In wide area, 71% of the offered load can be transferred through end-to-end circuits
With software signaling, this number is 51%
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33. Hardware-accelerated signaling and network survivability
Two approaches for network survivability
Protection requires pre-allocated resources and reacts to failure rapidly
SONET APS requires 100% resource redundancy (1+1) and can recover in 50ms
Restoration dynamically sets up a secondary path after a failure - less resource redundancy but longer recovery delay
Hardware-accelerated signaling
Less resource redundancy and acceptable recovery delay (<200ms)
A sample network with 13 nodes and 22 links
Recover from one link failure in 200ms with 9% extra resources
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34. Outline Background and problem statement
OCSP: a performance-oriented signaling protocol and its hardware implementation
A subset of RSVP-TE signaling protocol and its hardware implementation
Comparison of signaling transport options
Implications of hardware-accelerated signaling
Conclusions and future work
2018/12/2

35. Conclusions and future work
Hardware-accelerated signaling is feasible and our implementation demonstrates a 100x-1000x speedup vis-à-vis software implementations
Applications like large file transfer and network restoration can benefit from hardware signaling and a well-devised signaling transport scheme
Future work
Finish the design and testing of the prototype board
New architectures and applications that can fully utilize the benefit of hardware-accelerated signaling
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36. Thank you!
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