1. Pulse Definitions
Actual pulses are not ideal but are described by the rise time, fall time, amplitude, and other characteristics.
-In an ideal pulse, rise time and fall time are 0.

2. AND OR NOT Basic Logic Functions
Output is high only if all inputs are high.
AND OR
Output is high only if one or more inputs are high.
-We’ll study this in much more detail in the weeks ahead. Logic gates are the building blocks of digital circuits. Gates are composed of resistors, transistors, and diodes, but we usually ignore this internal structure and only care about what output level it produces for different combinations of inputs.
-Show circuit from Lab 6.
NOT
Output is the opposite of the input.

3. Unused Gate Inputs (Floyd, p. 143)
-Unconnected pins can act as antennas, picking up noise and leading to unpredictable behavior.
-In the case of tying TTL HIGH, the resistor provides protection against power-supply spikes.

4. Domain of an expression
The domain of a Boolean expression is the set of variables contained in the expression in either complemented or uncomplemented form.
Examples: The domain of AB + C(DE + F) is the set of variables A, B, C, D, E, F.
The domain of ABC + AC is the set of variables A, B, C.
-Our first example has a domain of A, B, C. Second example’s domain is A, B, C, D.

5. Example Solution SOP Standard form
In SOP standard form, every variable in the domain must appear in each product term in the expression. This form is useful for constructing truth tables and for simplifying expressions.
To convert an SOP expression to SOP standard form, multiply each nonstandard product term by a term made up of the sum of the missing variable and its complement.
Example
-For most expressions, SOP Standard form is definitely not the simplest form of the expression.
-For our first example, SOP standard = A’BC’ + A’B’C’ + AB’C’ (3 terms). For second example, ABC’D’ + ABC’D + ABCD’ + ABCD + A’BCD + A’B’CD + A’BCD’ (7 terms)
Convert X = A B + A B C to SOP standard form.
Solution
The first term does not include the variable C. Therefore, multiply it by (C + C), which = 1:
X = A B (C + C) + A B C
= A B C + A B C + A B C

6. Karnaugh maps
Cells are usually labeled using 0’s and 1’s to represent the variable and its complement.
The numbers are entered in gray code, to force adjacent cells to be different by only one variable.
Gray code
Ones are read as the true variable and zeros are read as the complemented variable.

7. Example Solution SOP form
The Logic Converter in Multisim can convert a circuit into SOP form.
Use Multisim to view the logic for the circuit in SOP form.
Example
Solution
Click the truth table to logic button on the Logic Converter.
See next slide…

8. SOP form
-Use it to check our two examples from this lecture.
SOP form

9. The truth table for an exclusive-OR gate is
Exclusive-OR Logic
The truth table for an exclusive-OR gate is
Notice that the output is HIGH whenever A and B disagree.
The Boolean expression is
X = AB + AB
The circuit can be drawn as A
Symbols: X
Distinctive shape Rectangular outline B

10. The truth table for an exclusive-NOR gate is
Exclusive-NOR Logic
The truth table for an exclusive-NOR gate is
Notice that the output is HIGH whenever A and B agree.
The Boolean expression is
X = AB + AB
The circuit can be drawn as A
Symbols: X B
Distinctive shape Rectangular outline

11. Pulsed Waveforms
For combinational circuits with pulsed inputs, the output can be predicted by developing intermediate outputs and combining the result. For example, the circuit shown can be analyzed at the outputs of the OR gates: A A G1 B B G3 C C G2 D D G1 G2 G3

12. Pulsed Waveforms
Inputs
Output
Alternatively, you can develop the truth table for the circuit and enter 0’s and 1’s on the waveforms. Then read the output from the table.
A B C D X 1 A G1 B G3 C G2 D A B C D G3

13. GAL22V10 Programmable Logic Device
Manufactured by Lattice Semiconductor Corporation.
DIP has 24 pins:
VCC on pin 24
Ground on pin 12
Pins 1 through 11 and pin 13 are inputs
Pins 14 through 23 can be configured as inputs or as outputs.
Data sheet (on course website)

14. WinCUPL Software Created by Atmel Corporation.
Can be used to program many different PLDs, including the GAL22V10.
Free download and user’s manual at

15. Needham EMP-11 Universal Device Programmer
Manufactured by Needham Electronics (now out of business).
Can be used to “burn” designs into many different PLDs, including the GAL22V10.

16. Steps to Programming a PLD
Using WinCUPL, create a file describing your design. (File extension = .pld)
Using WinCUPL, compile this file to create a JEDEC file. (File extension = .jed)
Transfer the JEDEC file to the podium computer, and use EMP-11 to “burn” the design onto a GAL22V10 chip.
On the breadboard, test your design by wiring the GAL22V10 chip’s inputs to switches and its outputs to LEDs.

17. Step 1: Describing your design in WinCUPL
Start WinCUPL program.
Click File > New > Design File.
In Name box, type SimpleExample. In Designer box, type your name. In Device box, type g22v10. Click OK.
Enter the number of Input Pins in your design. Click OK. Enter the number of Output Pins in your design. Click OK. For Pinnodes, enter 0. Click OK.
In INPUT PINS section of the file, assign names (such as A, B, C) to as many of the input pins as you need.
In OUTPUT PINS section of the file, assign names (such as X, Y, Z) to as many of the output pins as you need.
Below OUTPUT PINS section of the file, type Boolean equations, using & for AND, # for Or, and ! (in front of a variable) for NOT. For example:
X = !A&!B&!C # A&B&C; Y = !(A#B#C);
Show effect of leaving off semicolons; reversing pin #s and names; using wrong symbol for OR.

18. Step 2: Compiling your file in WinCUPL
Save your file using File > Save. (This filename will end in .pld)
Click Run > Device Dependent Compile.
You should get a message telling you that compilation was successful.
Look on your disk in the same folder where you saved your .pld file, and you should find a new file ending in .jed (and some other new files too).

19. Example Solution Parity Generators/Checkers
Parity is an error detection method that uses an extra bit appended to a group of bits to force them to be either odd or even. In even parity, the total number of ones is even; in odd parity the total number of ones is odd.
Example
The ASCII letter S is Show the parity bit for the letter S with odd and even parity.
Solution
S with odd parity =
S with even parity =

20. Signed Binary Integers
The book discusses three possible ways of representing signed binary integers:
In sign-magnitude form (the easiest way for humans to understand).
In 1’s complement form.
In 2’s complement form (the way that computers use, so the most important one to understand).
In all three ways, the MSB is the sign bit: if it’s 1, then the integer is negative, and if it’s 0, then the integer is positive or zero.
-From now on, whenever we talk about signed integers we’ll assume that we’re using 2’s complement form (rather than sign-magnitude form or 1’s complement form).

21. One’s Complement
The one’s complement of a binary integer is just the inverse of the digits. To form the one’s complement, change all 0’s to 1’s and all 1’s to 0’s.
For example, the one’s complement of is
In digital circuits, the one’s complement is formed by using inverters:

22. Recall that the 1’s complement of 11001010 is
Two’s Complement
The two’s complement of a binary integer is found by adding 1 to the one’s complement.
Recall that the 1’s complement of is
(1’s complement) +1
To form the 2’s complement, add 1:
(2’s complement) 1

23. Two’s Complement: A Shortcut Method
Here’s an easier (for humans) way to find the two’s complement of a binary integer:
Starting at the right-hand end (LSB), write the bits as they are up to and including the first 1.
Then write the 1’s complement of the remaining bits.
-Do this with previous example: 2’s complement of is
-Another example: Find 2’s complement of =

24. Signed Binary Integers: Two’s Complement Form
In two’s complement form, positive integers and zero are written in the usual way, and a negative integer is the 2’s complement of the corresponding positive integer.
For example, using 8 bits, in two’s complement form, the positive integer 58 is written as
The negative integer -58 is written as
Sign bit
Magnitude bits
Another example: +23 = ?, -23 =?

25. Example Solution Signed Binary Integers: Two’s Complement Form
An easy way to read a signed integer in two’s complement form is to assign the sign bit a column weight of (for an 8-bit number). Then add the usual column weights for the 1’s.
Assuming that the sign bit = -128, show that = -58 as a two’s complement signed number:
Example
Do a few examples.
Solution
Column weights:
= -58

26. CAUTION: Beware of Overflow Situations
If the number of bits required for the answer is too great, overflow will occur. This can occur only if both numbers have the same sign. The overflow will be indicated by an incorrect sign bit. In such cases, the answer is incorrect and must be rejected.
Two examples are:
= +64
= +65
= -127
= -127
Discard carry
= +2
Wrong! The sign bit has changed, so the answer is incorrect.

27. Positive Logic versus Negative Logic
Any gate or logic circuit can be looked at from either an active-HIGH perspective (“positive logic”) or an active-LOW perspective (“negative logic”).
Example: The gates on a 7408 chip can be considered either positive-AND gates or negative-OR gates.
Data Sheet: 7408

28. BCD Decoder/Driver
The 74LS47 features leading zero suppression, which blanks unnecessary leading zeros but keeps significant zeros as illustrated here. The BI/RBO output is connected to the RBI input of the next decoder.
Blanked
Blanked
Depending on the display type, current limiting resistors may be required.

29. BCD Decoder/Driver
Trailing zero suppression blanks unnecessary trailing zeros to the right of the decimal point as illustrated here. The RBI input is connected to the BI/RBO output of the following decoder.
Decimal point
Blanked
Blanked

30. Unused Inputs
Recall that unused inputs should not be left floating. Either tie them to VCC or tie them to ground. 30

31. Outline of Today’s Material
Cascading Counters
Counter Decoding
Truncated Sequences
Dependency Notation on Logic Symbols 31

32. Outline Cascading Counters Counter Decoding Truncated Sequences
Dependency Notation on Logic Symbols 32

33. Question Counter Decoding
Decoding is the detection of a binary number and can be done with an AND gate.
-What kind of counter is this?
Question
What number is decoded by this gate?

34. Example Solution Counter Decoding
Show how to decode state 5 with an active LOW output.
What kind of counter?
Solution
Notice that a NAND gate was used to give the active LOW output.

35. Partial Decoding
The decade counter shown above incorporates partial decoding (looking at only the MSB and one other bit) to detect This was possible because this is the first occurrence of this combination in the sequence.
Detects 1010 by looking only at two bits
CLK K0 J0 Q0 C J1 J2 K1 K2 Q1 Q2
HIGH J3 K3 Q3
What kind of counter?

36. Outline Cascading Counters Counter Decoding Truncated Sequences
Dependency Notation on Logic Symbols 36

37. Truncated Sequence (Review)
Last week we saw one way to truncate a counter’s sequence: by adding decoder logic that clears the counter back to zero when it reaches a certain count.
When we use this technique, we’re removing counts from the high end of the counter’s sequence.
Example: a four bit counter that counts from 0 to 9 and then recycles. (See next slide.)
-What MOD would this counter be? 37

38. Truncated Sequence
This counter uses partial decoding to recycle the count sequence to zero after the 1001 state.
CLK K0 J0 Q0 C J1 J2 K1 K2 Q1 Q2
HIGH J3 K3 Q3
CLR
-Variation on the basic counter, except extra gates force the count back to 0 before it gets all the way up to 15. This is called a truncated sequence. 38

39. Truncated Counters (Another Way)
When using a counter chip that has data inputs and a LOAD input, we can also remove counts from the low end of the counter’s sequence.
Example: a four-bit counter that counts from 6 to 15 and then recycles.
Do this by setting the data inputs equal to 6 (=01102), and connect Terminal Count output back to the LOAD input.
-What MOD would this counter be? 39

40. Truncated Counter (Continued)
Show connections to make this recycle from 15 back to 6:
Recall from last week that the 74163’s ~LOAD input is a synchronous input. 40

41. Extending This Idea for Truncated Counters (Example from book)
-Without the RCO-LOAD connection, what would this counter’s MOD be?
-As shown below, what is its MOD?
-What hex value should we load to make it MOD-10,000?
-This is Fig 8-42 on p. 448 41

42. Outline Cascading Counters Counter Decoding Truncated Sequences
Dependency Notation on Logic Symbols 42

43. Dependency Notation on Logic Symbols
Dependency notation allows the logical operation of a device to be determined from its logic symbol.
Common control block
CTR DIV 16
CLR
5CT = 0 D0 D1 D2 D3
LOAD M1 M2
RCO
ENT G3
ENP G4
CLR
CLK
C5/2,3,4
LOAD
CTR DIV 16
ENT
RCO D0
ENP Q0
CLK C D1 Q1 D2 Q2 D3 Q3 Q0 Q1 Q2 Q3

44. Dependency Notation (Cont.)
If you know how to read dependency notation, you can quickly learn a lot of details about a chip’s operation by looking at its logic symbol.
Example: On this datasheet, compare logic symbols for and to find a small (but important) difference in their operation. 44

45. Dependency Notation (Cont.)
For details on how to read dependency notation, see this overview of IEEE Standard 45

46. Parallel in/Serial out Shift Register
Shift registers can be used to convert parallel data to serial form. A logic diagram for this type of register is shown: D0 D1 D2 D3
SHIFT/LOAD
Serial data out Q0 Q1 Q2 Q3
CLK

47. Cascading Counters
Most counter chips are 4-bit counters, with a modulus of 16 or less.
To get larger moduli, you cascade two or more counter chips together.
When you cascade counters, their moduli multiply, not add.
Example: If you cascade a MOD-10 counter with a MOD-16 counter, you get a MOD-160 counter.
The connections for cascading counters differ depending on whether you’re using asynchronous counters or synchronous counters. 47

48. Cascading asynchronous counters
-What MOD is this counter? 48

49. Cascading Synchronous Counters
For cascading, most synchronous counter chips have one or more enable input pins and one or more terminal-count output pins.
General idea: one chip’s terminal-count output drives the next chip’s enable input. (See next slide).
These pins go by various names such as :
CTEN, CEN, ENT, ENP, for the enable inputs
TC, CO, RCO, MAX, MAX/MIN for the terminal- count outputs.
Also, depending on the chip, these pins may be active-high or active-low. 49

50. Example Solution Cascading synchronous counters
For synchronous IC counters, the next counter is enabled only when the terminal count of the previous stage is reached.
HIGH
CLK Q0 Q1 Q2 C
Counter 1
Counter 2
CTEN
CTR DIV 16 Q3 TC
fin
fout
Explain operation.
Some variations to this basic idea:
-May have more than one enable (‘160).
-Alternate names for enable (ENT, ENP) and TC (RCO, CO, BO) pins.
-Enable and/or TC pins may be active low instead of active-high.
What is the modulus of these cascaded counters?
If fin =100 kHz, what is fout?
Example
Solution
a) Each counter divides the frequency by 16. Thus the modulus is 162 = 256.
b) The output frequency is 100 kHz/256 = 391 Hz 50