12/2/2018 CPE 631 Lecture 11: Instruction Level Parallelism and Its Dynamic Exploitation Aleksandar Milenković, milenka@ece.uah.edu Electrical and Computer.

12/2/2018 CPE 631 Lecture 11: Instruction Level Parallelism and Its Dynamic Exploitation Aleksandar Milenković, Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovich

Techniques to exploit parallelism
12/2/2018 Techniques to exploit parallelism Technique (Section in the textbook) Reduces Forwarding and bypassing (Section A.2) Data hazard (DH) stalls Delayed branches (A.2) Control hazard stalls Basic dynamic scheduling (A.8) DH stalls (RAW) Dynamic scheduling with register renaming (3.2) WAR and WAW stalls Dynamic branch prediction (3.4) CH stalls Issuing multiple instruction per cycle (3.6) Ideal CPI Speculation (3.7) Data and control stalls Dynamic memory disambiguation (3.2, 3.7) RAW stalls w. memory Loop Unrolling (4.1) Basic compiler pipeline scheduling (A.2, 4.1) DH stalls Compiler dependence analysis (4.4) Ideal CPI, DH stalls Software pipelining and trace scheduling (4.3) Ideal CPI and DH stalls Compiler speculation (4.4) Ideal CPI, and D/CH stalls 02/12/2018 UAH-CPE631 Aleksandar Milenkovich

Tomasulo-based FPU for MIPS
12/2/2018 Tomasulo-based FPU for MIPS From Instruction Unit FP Registers From Mem FP Op Queue Load Buffers Load1 Load2 Load3 Load4 Load5 Load6 Store Buffers Store1 Store2 Store3 Add1 Add2 Add3 Mult1 Mult2 Resolve RAW memory conflict? (address in memory buffers) Integer unit executes in parallel Reservation Stations To Mem FP adders FP multipliers Common Data Bus (CDB) 02/12/2018 UAH-CPE631 Aleksandar Milenkovich

Reservation Station Components
12/2/2018 Reservation Station Components Op: Operation to perform in the unit (e.g., + or –) Vj, Vk: Value of Source operands Store buffers has V field, result to be stored Qj, Qk: Reservation stations producing source registers (value to be written) Note: Qj/Qk=0 => source operand is already available in Vj /Vk Store buffers only have Qi for RS producing result Busy: Indicates reservation station or FU is busy Register result status—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions that will write that register. What you might have thought 1. 4 stages of instruction executino 2.Status of FU: Normal things to keep track of (RAW & structura for busyl): Fi from instruction format of the mahine (Fi is dest) Add unit can Add or Sub Rj, Rk - status of registers (Yes means ready) Qj,Qk - If a no in Rj, Rk, means waiting for a FU to write result; Qj, Qk means wihch FU waiting for it 3.Status of register result (WAW &WAR)s: which FU is going to write into registers Scoreboard on 6600 = size of FU 6.7, 6.8, 6.9, 6.12, 6.13, 6.16, 6.17 FU latencies: Add 2, Mult 10, Div 40 clocks 02/12/2018 UAH-CPE631 Aleksandar Milenkovich

Three Stages of Tomasulo Algorithm
1. Issue—get instruction from FP Op Queue If reservation station free (no structural hazard), control issues instr & sends operands (renames registers) 2. Execute—operate on operands (EX) When both operands ready then execute; if not ready, watch Common Data Bus for result 3. Write result—finish execution (WB) Write it on Common Data Bus to all awaiting units; mark reservation station available Normal data bus: data + destination (“go to” bus) Common data bus: data + source (“come from” bus) 64 bits of data + 4 bits of Functional Unit source address Write if matches expected Functional Unit (produces result) Does the broadcast Example speed: 2 clocks for Fl .pt. +,-; 10 for * ; 40 clks for / 02/12/2018 UAH-CPE631

Tomasulo Example Instruction stream 3 Load/Buffers FU count
down 3 FP Adder R.S. 2 FP Mult R.S. Clock cycle counter 02/12/2018 UAH-CPE631

Tomasulo Example Cycle 1
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Note: Can have multiple loads outstanding 02/12/2018 UAH-CPE631

Note: registers names are removed (“renamed”) in Reservation Stations; MULT issued Load1 completing; what is waiting for Load1? 02/12/2018 UAH-CPE631

Load2 completing; what is waiting for Load2? 02/12/2018 UAH-CPE631

Timer starts down for Add1, Mult1 02/12/2018 UAH-CPE631

Issue ADDD here despite name dependency on F6? 02/12/2018 UAH-CPE631

Add1 (SUBD) completing; what is waiting for it? 02/12/2018 UAH-CPE631

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Add2 (ADDD) completing; what is waiting for it? 02/12/2018 UAH-CPE631

Write result of ADDD here? All quick instructions complete in this cycle! 02/12/2018 UAH-CPE631

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Mult1 (MULTD) completing; what is waiting for it? 02/12/2018 UAH-CPE631

Just waiting for Mult2 (DIVD) to complete 02/12/2018 UAH-CPE631

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Mult2 (DIVD) is completing; what is waiting for it? 02/12/2018 UAH-CPE631

Once again: In-order issue, out-of-order execution and out-of-order completion. 02/12/2018 UAH-CPE631

Many associative stores (CDB) at high speed
Tomasulo Drawbacks Complexity delays of 360/91, MIPS 10000, Alpha 21264, IBM PPC 620 in CA:AQA 2/e, but not in silicon! Many associative stores (CDB) at high speed Performance limited by Common Data Bus Each CDB must go to multiple functional units  high capacitance, high wiring density Number of functional units that can complete per cycle limited to one! Multiple CDBs  more FU logic for parallel assoc stores Non-precise interrupts! We will address this later 02/12/2018 UAH-CPE631

This time assume Multiply takes 4 clocks
Tomasulo Loop Example Loop: LD F0 0(R1) MULTD F4 F0 F2 SD F4 0 R1 SUBI R1 R1 #8 BNEZ R1 Loop This time assume Multiply takes 4 clocks Assume 1st load takes 8 clocks (L1 cache miss), 2nd load takes 1 clock (hit) To be clear, will show clocks for SUBI, BNEZ Reality: integer instructions ahead of Fl. Pt. Instructions Show 2 iterations 02/12/2018 UAH-CPE631

Value of Register used for address, iteration control
Loop Example Iter- ation Count Added Store Buffers Instruction Loop Value of Register used for address, iteration control 02/12/2018 UAH-CPE631

Loop Example Cycle 1 02/12/2018 UAH-CPE631

Loop Example Cycle 3 Implicit renaming sets up data flow graph
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Loop Example Cycle 20 Once again: In-order issue, out-of-order execution and out-of-order completion. 02/12/2018 UAH-CPE631

Why can Tomasulo overlap iterations of loops?
Register renaming Multiple iterations use different physical destinations for registers (dynamic loop unrolling) Reservation stations Permit instruction issue to advance past integer control flow operations Also buffer old values of registers - totally avoiding the WAR stall that we saw in the scoreboard Other perspective: Tomasulo building data flow dependency graph on the fly 02/12/2018 UAH-CPE631

Tomasulo’s scheme offers 2 major advantages
(1) the distribution of the hazard detection logic distributed reservation stations and the CDB If multiple instructions waiting on single result, & each instruction has other operand, then instructions can be released simultaneously by broadcast on CDB If a centralized register file were used, the units would have to read their results from the registers when register buses are available. (2) the elimination of stalls for WAW and WAR hazards 02/12/2018 UAH-CPE631

What about Precise Interrupts?
Tomasulo had: In-order issue, out-of-order execution, and out-of-order completion Need to “fix” the out-of-order completion aspect so that we can find precise breakpoint in instruction stream 02/12/2018 UAH-CPE631

Relationship between precise interrupts and speculation
Speculation is a form of guessing Important for branch prediction: Need to “take our best shot” at predicting branch direction If we speculate and are wrong, need to back up and restart execution to point at which we predicted incorrectly: This is exactly same as precise exceptions! Technique for both precise interrupts/exceptions and speculation: in-order completion or commit 02/12/2018 UAH-CPE631

HW support for precise interrupts
Need HW buffer for results of uncommitted instructions: reorder buffer 3 fields: instr, destination, value Use reorder buffer number instead of reservation station when execution completes Supplies operands between execution complete & commit (Reorder buffer can be operand source => more registers like RS) Instructions commit Once instruction commits, result is put into register As a result, easy to undo speculated instructions on mispredicted branches or exceptions Reorder Buffer FP Op Queue FP Regs Res Stations Res Stations FP Adder FP Adder 02/12/2018 UAH-CPE631

Four Steps of Speculative Tomasulo Algorithm
1. Issue—get instruction from FP Op Queue If reservation station and reorder buffer slot free, issue instr & send operands & reorder buffer no. for destination (this stage sometimes called “dispatch”) 2. Execution—operate on operands (EX) When both operands ready then execute; if not ready, watch CDB for result; when both in reservation station, execute; checks RAW (sometimes called “issue”) 3. Write result—finish execution (WB) Write on Common Data Bus to all awaiting FUs & reorder buffer; mark reservation station available. 4. Commit—update register with reorder result When instr. at head of reorder buffer & result present, update register with result (or store to memory) and remove instr from reorder buffer. Mispredicted branch flushes reorder buffer (sometimes called “graduation”) 02/12/2018 UAH-CPE631

What are the hardware complexities with reorder buffer (ROB)?
How do you find the latest version of a register? (As specified by Smith paper) need associative comparison network Could use future file or just use the register result status buffer to track which specific reorder buffer has received the value Need as many ports on ROB as register file Reorder Buffer FP Op Queue FP Adder Res Stations FP Regs Compar network Reorder Table Dest Reg Result Exceptions? Valid Program Counter 02/12/2018 UAH-CPE631

Summary Reservations stations: implicit register renaming to larger set of registers + buffering source operands Prevents registers as bottleneck Avoids WAR, WAW hazards of Scoreboard Allows loop unrolling in HW Not limited to basic blocks (integer units gets ahead, beyond branches) Today, helps cache misses as well Don’t stall for L1 Data cache miss (insufficient ILP for L2 miss?) Lasting Contributions Dynamic scheduling Register renaming Load/store disambiguation 360/91 descendants are Pentium III; PowerPC 604; MIPS R10000; HP-PA 8000; Alpha 21264 02/12/2018 UAH-CPE631

Branch Prediction Aleksandar Milenković, milenka@ece.uah.edu
12/2/2018 Branch Prediction Aleksandar Milenković, Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovich

The Case for Branch Prediction
Dynamic scheduling increases the amount of ILP => control dependence becomes the limiting factor Multiple issue processors Branches will arrive up to N times faster in an n-issue processor Amdahl’s Law => relative impact of the control stalls will be larger with the lower potential CPI in an n-issue processor What have we done? Static schemes for dealing with branches – compiler optimizes the the branch behavior by scheduling it at compile time 02/12/2018 UAH-CPE631

7 Branch Prediction Schemes
1-bit Branch-Prediction Buffer 2-bit Branch-Prediction Buffer Correlating Branch Prediction Buffer Tournament Branch Predictor Branch Target Buffer Integrated Instruction Fetch Units Return Address Predictors 02/12/2018 UAH-CPE631

Basic Branch Prediction (1)
12/2/2018 Basic Branch Prediction (1) Performance = ƒ(accuracy, cost of misprediction) Branch History Table: a small table of 1-bit values indexed by the lower bits of PC address Says whether or not branch taken last time Useful only to reduce branch delay when it is longer than the time to compute the possible target PC No address check – BHT has no address tags, so the prediction bit may have been put by another branch that has the same low-order bits Prediction is a hint, assumed to be correct – fetching begins in the predicted direction; if it turns out to be wrong, the prediction bit is inverted and stored back 02/12/2018 UAH-CPE631 Aleksandar Milenkovich

Basic Branch Prediction (2)
12/2/2018 Basic Branch Prediction (2) Problem: in a loop, 1-bit BHT will cause 2 mispredictions (avg is 9 iterations before exit): End of loop case, when it exits instead of looping as before First time through loop on next time through code, when it predicts exit instead of looping Only 80% accuracy even if loop 90% of the time Ideally for highly regular branches, the accuracy of predictor = taken branch frequency Solution: use two-bit prediction schemes 02/12/2018 UAH-CPE631 Aleksandar Milenkovich

States in a two-bit prediction scheme
2-bit Scheme States in a two-bit prediction scheme Red: stop, not taken Green: go, taken Adds hysteresis to decision making process T NT Predict Taken Predict Taken T T NT NT Predict Not Taken Predict Not Taken T NT 02/12/2018 UAH-CPE631

Note: Does this scheme help for simple MIPS?
BHT Implementation 1) Small, special “cache” accessed with the instruction address during the IF pipe stage 2) Pair of bits attached to each block in the instruction cache and fetched with the instruction How many branches per instruction? Complexity? Instruction is decoded as branch, and branch is predicted as taken => fetch from the target as soon as the PC is known Note: Does this scheme help for simple MIPS? 02/12/2018 UAH-CPE631

How to improve prediction accuracy?
BHT Performance Prediction accuracy of 2-bit predictor with 4096 entries is ranging from over 99% to 82% or misprediction rate of 1% to 18% Real impact on performance: prediction accuracy + branch cost + branch frequency How to improve prediction accuracy? Increase the size of the buffer (number of entries) Increase the accuracy for each prediction (increase the number of bits) Both have limited impact! 02/12/2018 UAH-CPE631

Case for Correlating Predictors
subi R3, R1, #2 bnez R3, L1 ; b1 add R1, R0, R0 L1: subi R3, R1, #2 bnez R3, L2 ; b2 add R2, R0, R0 L2: sub R3, R1, R2 beqz R3, L3 ; b3 Basic two-bit predictor schemes use recent behavior of a branch to predict its future behavior Improve the prediction accuracy look also at recent behavior of other branches if (aa == 2) aa = 0; if (bb == 2) bb = 0; if (aa != bb) { } b3 is correlated with b1 and b2; If b1 and b2 are both untaken, then b3 will be taken. => Use correlating predictors or two-level predictors. 02/12/2018 UAH-CPE631

An Example if (d == 0) d = 1; if (d == 1) { ... } bnez R1, L1 ; b1
Initial value of d d==0? b1 Value of d before b2 d==1? b2 Yes NT 1 No T 2 bnez R1, L1 ; b1 addi R1, R0, #1 L1: subi R3, R1, #1 bnez R3, L2 ; b2 ... L2: ... => if b1 is NT, then b2 is NT Behavior of one-bit Standard Predictor initialized to not taken; d alternates between 0 and 2. d=? b1 prediction b1 action New b1 prediction b2 prediction b2 action new b2 prediction 2 NT T => All branches are mispredicted 02/12/2018 UAH-CPE631

Prediction if last branch NT Prediction if last branch T
An Example Introduce one bit of correlation Each branch has two separate prediction bits: one prediction assuming the last branch executed was not taken, and another prediction assuming it was taken Prediction bits Prediction if last branch NT Prediction if last branch T NT/NT NT NT/T T T/NT T/T Behavior of one-bit predictor with one bit of correlation initialized to NT/NT; Assume last branch NT d=? b1 prediction b1 action New b1 prediction b2 prediction b2 action new b2 prediction 2 NT/NT T T/NT NT/T NT ? NT b1 T b2 => Only misprediction is on the first iteration 02/12/2018 UAH-CPE631

(1, 1) predictor from the previous example
Uses the behavior of the last branch to choose from among a pair of one-bit branch predictors (m, n) predictor Uses the behavior of the last m branches to choose from among 2m predictors, each of which is a n-bit predictor for a single branch Global history of the most recent branches can be recorded in an m-bit shift register (each bit records whether a branch is taken or not) 02/12/2018 UAH-CPE631

2-bits per branch local predictors (01 = not taken then taken)
Branch address (4 bits) 2-bit global history to choose from among 4 predictors for each branch address 2-bit local predictor 2-bits per branch local predictors Prediction (2, 2) predictor is implemented as a linear memory array that is 2 bits wide; the indexing is done by concatenating the global history bits and the number of required bits from the branch address. 2-bit global branch history (01 = not taken then taken) 02/12/2018 UAH-CPE631

Fair Predictor Comparison
Compare predictors that use the same number of state bits number of state bits for (m, n): 2m*n*(number of prediction entries) number of state bits for (0, n): n*(number of prediction entries) Example: How many branch selected entries are in a (2,2) predictor that has a total of 8K state bits => 22*2*(number of entries) = 8K => number of branch selected entries is 1K 02/12/2018 UAH-CPE631

Accuracy of Different Schemes
4096 Entries 2-bit BHT Unlimited Entries 2-bit BHT 1024 Entries (2,2) BHT Frequency of Mispredictions 02/12/2018 UAH-CPE631

Re-evaluating Correlation
Several of the SPEC benchmarks have less than a dozen branches responsible for 90% of taken branches: program branch % static # = 90% compress 14% eqntott 25% gcc 15% mpeg 10% real gcc 13% Real programs + OS more like gcc Small benefits beyond benchmarks for correlation? problems with branch aliases? 02/12/2018 UAH-CPE631

Predicated Execution Avoid branch prediction by turning branches into conditionally executed instructions: if (x) then A = B op C else NOP If false, then neither store result nor cause exception Expanded ISA of Alpha, MIPS, PowerPC, SPARC have conditional move; PA-RISC can annul any following instr. IA-64: 64 1-bit condition fields selected so conditional execution of any instruction This transformation is called “if-conversion” Drawbacks to conditional instructions Still takes a clock even if “annulled” Stall if condition evaluated late Complex conditions reduce effectiveness; condition becomes known late in pipeline x A = B op C 02/12/2018 UAH-CPE631

Predicated Execution: An Example
if (R1 > R2) { R3 = R1 + R2; R4 = R2 + 1; } else R3 = R1 – R2; SGT R5, R1, R2 BZ L1 ADD R3, R1, R2 ADDI R4, R2, #1 J After L1: SUB R3, R1, R2 After: ... CMP R1, R2 ; set condition code ADD.GT R3, R1, R2 ADDI.GT R4, R2, #1 SUB.LE R3, R1, R2 02/12/2018 UAH-CPE631

Mispredict because either:
BHT Accuracy Mispredict because either: Wrong guess for that branch Got branch history of wrong branch when index the table 4096 entry table programs vary from 1% misprediction (nasa7, tomcatv) to 18% (eqntott), with spice at 9% and gcc at 12% For SPEC92, 4096 about as good as infinite table 02/12/2018 UAH-CPE631

Tournament Predictors
Motivation for correlating branch predictors is 2-bit predictor failed on important branches; by adding global information, performance improved Tournament predictors use several levels of branch prediction tables together with an algorithm for choosing among predictors Hopes to select right predictor for right branch 02/12/2018 UAH-CPE631

Tournament Predictor in Alpha 21264 (1)
4K 2-bit counters to choose from among a global predictor and a local predictor 0/0 Use Ls Use Gs Use L Use G 1/0 1/1 0/1 Legend: 0/0 – Prediction for L is incorrect, Prediction for G is incorrect 02/12/2018 UAH-CPE631

Tournament Predictor in Alpha 21264 (2)
Global predictor also has 4K entries and is indexed by the history of the last 12 branches; each entry in the global predictor is a standard 2-bit predictor 12-bit pattern: ith bit 0 => ith prior branch not taken; ith bit 1 => ith prior branch taken; Local predictor consists of a 2-level predictor: Top level a local history table consisting of bit entries; each 10-bit entry corresponds to the most recent 10 branch outcomes for the entry. 10-bit history allows patterns 10 branches to be discovered and predicted. Next level Selected entry from the local history table is used to index a table of 1K entries consisting a 3-bit saturating counters, which provide the local prediction Total size: 4K*2 + 4K*2 + 1K*10 + 1K*3 = 29K bits! (~180,000 transistors) 02/12/2018 UAH-CPE631

% of predictions from local predictor in Tournament Prediction Scheme
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Accuracy of Branch Prediction
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Accuracy v. Size (SPEC89) 02/12/2018 UAH-CPE631

Branch Target Buffers Prediction in DLX
need to know from what address to fetch at the end of IF need to know whether the as-yet-undecoded instruction is branch, and if so, what the next PC should be Branch prediction cache that stores the predicted address for the next instruction after a branch is called a branch target buffer (BTB) 02/12/2018 UAH-CPE631

BTB Branch PC Predicted PC PC of instruction FETCH =? Extra prediction state bits Yes: instruction is branch and use predicted PC as next PC No: branch not predicted, proceed normally (Next PC = PC+4) Keep only predicted-taken branches in BTB, since an untaken branch follows the same strategy as a nonbranch 02/12/2018 UAH-CPE631

Special Case Return Addresses
Register Indirect branch hard to predict address SPEC89 85% such branches for procedure return Since stack discipline for procedures, save return address in small buffer that acts like a stack: 8 to 16 entries has small miss rate 02/12/2018 UAH-CPE631

Pitfall: Sometimes bigger and dumber is better
21264 uses tournament predictor (29 Kbits) Earlier uses a simple 2-bit predictor with 2K entries (or a total of 4 Kbits) SPEC95 benchmarks, outperforms 21264 avg mispredictions per 1000 instructions 21164 avg mispredictions per 1000 instructions Reversed for transaction processing (TP)! 21264 avg. 17 mispredictions per 1000 instructions 21164 avg. 15 mispredictions per 1000 instructions TP code much larger & hold 2X branch predictions based on local behavior (2K vs. 1K local predictor in the 21264) 02/12/2018 UAH-CPE631

Dynamic Branch Prediction Summary
Prediction becoming important part of scalar execution Branch History Table: 2 bits for loop accuracy Correlation: Recently executed branches correlated with next branch. Either different branches Or different executions of same branches Tournament Predictor: more resources to competitive solutions and pick between them Branch Target Buffer: include branch address & prediction Predicated Execution can reduce number of branches, number of mispredicted branches Return address stack for prediction of indirect jump 02/12/2018 UAH-CPE631

12/2/2018 CPE 631 Lecture 11: Instruction Level Parallelism and Its Dynamic Exploitation Aleksandar Milenković, milenka@ece.uah.edu Electrical and Computer.

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12/2/2018 CPE 631 Lecture 11: Instruction Level Parallelism and Its Dynamic Exploitation Aleksandar Milenković, milenka@ece.uah.edu Electrical and Computer.

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Presentation on theme: "12/2/2018 CPE 631 Lecture 11: Instruction Level Parallelism and Its Dynamic Exploitation Aleksandar Milenković, milenka@ece.uah.edu Electrical and Computer."— Presentation transcript:

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