1. How NOT to design an ISA
x86

2. Key differences from MIPS
Limited registers (And special purpose)
Different branching capabilities
Every conceivable addressing mode
Almost every opcode under the sun
Multibyte encoding

3. Registers

4. Branching Normal branching: Explicit loop control: Hardware memcpy:
All-purpose “CMP” followed by flag-based branch: BGE, BLE, etc
Explicit loop control:
Place count in ECX and “LOOPZ”
Hardware memcpy:
Count in ECX, “REP MOVSW”
Hardware stack:
PUSH / POP
CALL / RET

5. Addressing modes Register: inc bx Immediate: mov cx, 10
Memory: mov cx, [address]
Register Indirect: mov cx, [bx]
Base Relative: mov cx, [bx+1]
Base Indexed: mov cx, [bx+si]
…and so on

6. Multibyte Encoding

7. So what were they thinking?
Architectural support for HLLs
Compilers would just be tiny syntax translators
No systematic study of that premise