1. DSPs for Future Wireless Base-Stations
Sridhar Rajagopal and Joseph Cavallaro
ECE Dept., Rice University
April 6, 2000

2. Overview Requirements for Future Base-Stations
Current DSP Implementations
Suggestions for Performance Acceleration
Questions for Ray Simar
Meeting with Ray Simar
12/2/2018

3. Evolution of Wireless Comm
First Generation
Voice
Second/Current Generation
Voice + Low-rate Data (9.6Kbps)
Third Generation +
Voice + High-rate Data (2 Mbps) + Multimedia
W-CDMA
Meeting with Ray Simar
12/2/2018

4. Communication System Uplink
Direct Path
Reflected Paths
Noise +MAI
User 1
User 2
Base Station
Meeting with Ray Simar
12/2/2018

5. Main Processing Blocks
Channel Estimation
Detection
Decoding
Meeting with Ray Simar
12/2/2018

6. No Multiuser Detection
Proposed Base-Station
TI's Wireless Basestation (
Meeting with Ray Simar
12/2/2018

7. Current DSP Implementation9 10 11 12 13 14 15
0.5 1
1.5 2
x 10 5
Number of Users
Data Rates
Data Rates for a typical DSP Implementation
Data Rate Requirement = 128 Kbps
Meeting with Ray Simar
12/2/2018

8. Complexity Algorithm Choice Limited by Complexity Main Features
Matrix based operations
High levels of parallelism
Bit level computations
32x32 problem size shown
Meeting with Ray Simar
12/2/2018

9. Reasons Sophisticated, Compute-Intensive Algorithms
Not enough MIPs/FLOPs performance
Unable to fully exploit pipelining or parallelism
Bit - level computations / Storage
Meeting with Ray Simar
12/2/2018

10. Our Approach Make algorithms computationally effective
without sacrificing error rate performance
Task Partitioning on Multiple Processing Elements
DSPs : Core
FPGAs : Application Specific / Bit-level Computations
VLSI Implementation
Meeting with Ray Simar
12/2/2018

11. Suggestions Bit-level storage / processing support
Registers / Memory / ALU
Efficient Matrix -Based operations
Matrix- Vector Multiply
Support for Complex-valued data
Efficient memory accesses
Pre-fetching Data
Meeting with Ray Simar
12/2/2018

12. Software Suggestions Limited OS Support Compiler Efficiency
No more Assembly!
Performance Analysis Tools
Meeting with Ray Simar
12/2/2018

13. Questions for Ray Simar
EPIC
DSP with FPGA core
Multimedia Extensions
In the future, what is a DSP ( as opposed to a GPP)?
Branch and Control in DSPs
Meeting with Ray Simar
12/2/2018

14. Questions for Ray Simar
Online Arithmetic
Truncated Multipliers
Meeting with Ray Simar
12/2/2018