1. Semiconductor Memories

2. Outline Concept/need of memory Parameters Types/classification
Basic features
Basic Cell circuits
Peripheral circuitry

3. Concept Data storage essential for processing Binary storage Switches
How do you implement this in Hardware?

4. Requirements Easy reading Easy Writing High density
Speed, more speed and still more speed

5. Memory Chip Configuration

6. Semiconductor Memory Classification
Non-Volatile
Read-Write Memory
Read-Write Memory
Read-Only Memory
Random
Non-Random
EPROM
Mask-Programmed
Access
Access 2 E
PROM
Programmable (PROM)
SRAM
FIFO
FLASH
LIFO
DRAM
Shift Register
CAM

7. RAM Random write and read operation for any cell Volatile data
Most of computer memory
DRAM
Low Cost
High Density
Medium Speed
SRAM
High Speed
Ease of use
Medium Cost

8. ROM Non-volatile Data Method of Data Writing Mask ROM PROM
Data written during chip fabrication
PROM
Fuse ROM: Non-rewritable
EPROM: Erase data by UV rays
EEPROM: Erase and write through electrical means
Speed 2-3 times slower than RAM
Upper limit on write operations
Flash Memory – High density, Low Cost

9. Basic Cells
SRAM
DRAM

10. Static CAM Memory Cell ••• ••• CAM Bit Word ••• Wired-NOR Match Line
int S
•••
•••

11. CAM in Cache Memory Hit Logic Address Decoder CAM SRAM ARRAY ARRAY
Input Drivers
Sense Amps / Input Drivers
Address
Tag
Hit
R/W
Data

12. ROM
EEPROM
Fuse ROM
Floating Gate

13. MOS NAND ROM V DD
Pull-up devices BL
[0] BL
[1] BL
[2] BL
[3] WL
[0] WL
[1] WL
[2] WL
[3]
All word lines high by default with exception of selected row

14. Non-Volatile Memories The Floating-gate transistor (FAMOS)D
Source
Drain t ox t ox n + p n +_
Substrate
Schematic symbol
Device cross-section

15. Floating-Gate Transistor Programming
20 V
10 V
5 V D S
Avalanche injection
0 V -
5 V D S
Removing programming
voltage leaves charge trapped
5 V -
2.5 V D S
Programming results in
higher V T .

16. A “Programmable-Threshold” Transistor

17. Periphery Decoders Sense Amplifiers Input/Output Buffers
Control / Timing Circuitry

18. Row Decoders Collection of 2M complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder

19. Hierarchical Decoders
Multi-stage implementation improves performance • • • WL 1 WL A A A A A A A A A A A A A A A A 1 1 1 1 2 3 2 3 2 3 2 3 • • •
NAND decoder using
2-input pre-decoders A A A A A A A A 1 1 3 2 2 3

20. Sense Amplifiers Idea: Use Sense Amplifer small s.a. transition inputC D V × I av =
make
V as small
as possible
small
large
Idea: Use Sense Amplifer
small
transition
s.a.
input
output

21. Sense Amp Operation D V (1) (0) t Sense amp activated
PRE BL
Sense amp activated
Word line activated

22. Differential Sense AmplifierV DD M M 3 4 y
Out
bit M M
bit 1 2 SE M 5
Directly applicable to SRAMs

23. Reliability and Yield