1. Digital Logic & Design
Dr. Waseem Ikram
Lecture 40

2. Memory array decoded by Row and Columns Decoders

3. Input/Output Data Circuit

4. Timing diagram of a Read Cycle

5. Timing diagram of a Write Cycle

6. Block diagram of a Synchronous Burst RAM

7. Burst Logic Circuit

8. Writing a 1 or 0 into the DRAM cell

9. Reading a 0 or 1 from the DRAM cell

10. Refreshing a DRAM cell

11. Circuit Diagram of a 1M x 1 DRAM
Memory Array
1024 rows x
1024 columns
Input/Output Buffers
and
Sense Amplifiers
Refresh
Counter
Control
Timing
Row
Decoder
Column
Data
Selector
Address
Latch D
OUT IN W / R E
RAS
CAS
Lines A -A 9

12. Recap Memory Latches and Flip-flops (small memory)
Computer Program Memory (large memory)
Data Storage
Bits, Nibbles, Bytes, Words
Memory Storage
Storage array of cells (stores 0 or 1)
Two dimensional array row & column

13. Recap Memory Organization Byte, Nibble, Bit
Memory Capacity and Density
Memory Block diagram and Signals
Address, Data, R/W and CS

14. Recap Static RAM cell implementation Internal structure of 8 x 4 RAM
16K x 8 RAM chip

15. Memory Row and column decoders in RAM (fig 1)
Input/Output RAM circuit (fig 2)
Read Cycle (fig 3)
Write Cycle (fig 4)

16. Sync. Burst SRAM & DRAM Sync. Burst SRAM (fig 5) Flow through SRAM
Pipelined SRAM
Burst Logic Circuitry (fig 6)
DRAM Structure (fig 7a)
Writing to DRAM (fig 7a)
Reading from DRAM (fig 7b)
Refreshing DRAM (fig 7c)
Address Multiplexing (fig 8)