1. Instructor: Alexander Stoytchev
CprE 281: Digital Logic
Instructor: Alexander Stoytchev

2. Serial Adder CprE 281: Digital Logic Iowa State University, Ames, IA
Copyright © Alexander Stoytchev

3. Administrative Stuff Homework 10 is out
It is due on Monday Dec 2, 2013

4. Administrative Stuff Extra Credit Homework #2 is out
Posted on the class web page
There are 4 problems
Due no later than the last lab for this semester
Submit your design on paper and demonstrate your circuit to the lab TAs using the boards in the lab.

5. Administrative Stuff Final Project
Posted on the class web page (Labs section)
Pick one of the 4 problems and solve it.
Your grade will not depend on which project you pick
By this Friday you need to select your project number and that number to your lab TAs

6. Sample E-mail Hello TAs,
I decided to pick problem number x for my final project in CprE 281.
Thanks,
[your name]

7. The general form of a synchronous sequential circuitW
Combinational
Combinational
Flip-flops Z
circuit
circuit Q
Clock
[ Figure 6.1 from the textbook ]

8. Moore Type W Combinational Combinational Flip-flops Z circuit circuitQ
Clock

9. Mealy Type W Combinational Combinational Flip-flops Z circuit circuitQ
Clock

10. Moore Mealy

11. Moore Mealy

12. Mealy
Moore

13. Mealy
Moore
This is delayed by
1 clock cycle

15. Figure 6.39. Block diagram for the serial adder.
Shift register s
Adder
FSM
Shift register
Shift register b
Sum = A + B B
Clock
Figure Block diagram for the serial adder.

16. Figure 6.40. State diagram for the serial adder FSM.

17. Figure 6.41. State table for the serial adder FSM.
Next state
Output s
Present
state ab
=00 01 10 11 00 01 10 11 G G G G H 1 1 H G H H H 1 1
Figure State table for the serial adder FSM.

18. Figure 6.42. State-assigned table for Figure 6.41.
Next state
Output
Present
state ab
=00 01 10 11 00 01 10 11 y Y s 1 1 1 1 1 1 1 1 1
Figure State-assigned table for Figure 6.41.

19. Figure 6.43. Circuit for the adder FSM in Figure 6.39.
Full b
adder Y y D Q
carry-out
Clock Q
Reset
Figure Circuit for the adder FSM in Figure 6.39.

20. Figure 6.44. State diagram for the Moore-type serial adder FSM.
Reset 11 01 00 G s = H s = 10 00 01 01 00 11 10 11 10 01 G s = 1 H s = 1 11 10 1 00 1
Figure State diagram for the Moore-type serial adder FSM.

21. Figure 6.45. State table for the Moore-type serial adder FSM.
Nextstate
Present
Output
state ab
=00 01 10 11 s G G G G H 1 1 G G G G H 1 1 1 1 H G H H H 1 1 H G H H H 1 1 1 1
Figure State table for the Moore-type serial adder FSM.

22. Figure 6.46. State-assigned table for Figure 6.45.
Nextstate
Present
Output
state ab
=00 01 10 11 y y s 2 1 Y Y 2 1 00 01 1 10 01 01 1 10 1 10 1 10 1 11 11 1 10 1 11 1
Figure State-assigned table for Figure 6.45.

23. Figure 6.47. Circuit for the Moore-type serial adder FSM.
Sum bit Y y 1 1 a D Q s
Full b
adder
Carry-out Q Y y 2 2 D Q
Clock Q
Reset
Figure Circuit for the Moore-type serial adder FSM.

24. Questions?

25. THE END