1. Signals - Drivers Value holder for a signal.
Created when signal assignments schedule some value at some future time.
Every signal has a separate driver.
Can be thought of as a source for a signal.
Driver maintains an ordered list of transactions.
Recollect transaction is assignment made to a signal.
Simulator uses the value of the signal stored in the driver.

2. Multiple Drivers
Signals may be updated in more than 1 process at the same time.
There may be more than 1 driver for the same signal, one for each process.
The values assigned may be same or different.
What to do if the values are different?

3. Multiple Drivers - Resolution
Resolution function is the solution.
This function resolves the value of the signal.
This function must resolve all possible pairs of values that two drivers may assign.
The signal being resolved is called the resolved signal.
The resolution function can be attached to
A signal directly or
A data-type itself.

4. Sequential Control StatementsIf
Case
Loop
Next
Exit
Inside loops

5. Sequential Control
Conditional Control
Iterative Control

6. Summary: Behavioral Descriptions in VHDL
A behavioral description consists of a set of processes.
A process represents the functionality of one or several devices.
It contains no information about the implementation of the devices.
A process will execute its statements one by one until a wait statement is encountered.
Behavioral descriptions are similar to high-level language programs.
VHDL is “ADA-like”
If the semantics of a VHDL construct matches an ADA construct, so does the syntax.

7. Modelling Combinational Logic
Conclusion:
There are very many ways to describe combinational logic.
Combinational logic can be specified using sequential statements

8. Modelling Sequential Logic
Sequential logic can be specified similarly to combinational

9. A D-latch example with set-up and hold checks
Here we illusgtrate assert and report only for simple circuit, but this is very useful for big circuits with complex timing

10. Modelling Finite State Machines
Previously we shown one process and two process description of sequential machines,
Now we have a 3 process example.
Used are also many process examples.

11. Modelling Finite State Machines (cont’d)
This is standard description
States encoded or not
Operations behavioral or signals only

12. Mixed Descriptions in VHDL
Structural, data-flow and behavioral descriptions can be mixed freely in an architecture body.
Signals are the “glue” which connects the different descriptions.
Ex.

13. If statement syntax If_statement ::= if condition then
sequence of sequential statements
{elsif condition then
sequence of sequential statements}
[else
sequence of sequential statements]
end if;
syntax

14. If Statements
Value of a Boolean Expression Determines Which Statements Are Executed
Expression must evaluate to TRUE or FALSE

15. Example of IF statement
Behavioral description of a counter using sequential statements, observe that each argument of IF evaluates to a Boolean value

16. Example of IF statement
Remember, order in elsif is important. We discussed this example in full detail earlier
Executed first

17. If statement: example of counter
The signal COUNT is of the OUT mode so it cannot be read.
entity IFSTMT is
port ( RSTn, CLK, EN, PL : in bit;
DATA : in integer range 0 to 31;
COUNT : out integer range 0 to 31);
end IFSTMT;
architecture RTL of IFSTMT is
signal COUNT_VALUE : integer range 0 to 31;
begin
p0 : process (RSTn, CLK)
if (RSTn = '0') then
COUNT_VALUE <= 0;
elsif (CLK'event and CLK = '1') then
if (PL = '1') then
COUNT_VALUE <= DATA;
elsif (EN = '1') then
if (COUNT_VALUE = 31) then
COUNT_VALUE <= 0;
else
COUNT_VALUE <=
COUNT_VALUE + 1;
end if;
end process;
COUNT <= COUNT_VALUE;
end RTL;
Asynchronous reset
A temporary signal COUNT_VALUE is used to calculate the COUNT value.
Then COUNT_VALUE is assigned to the output port COUNT outside the process.

18. This temporary signal is assigned in architecture not in process
If statement
REMEMBER THIS TYPICAL CONSTRUCTION:
The signal COUNT is of the OUT mode so it cannot be read.
A temporary signal COUNT_VALUE is used to calculate the COUNT value.
Then COUNT_VALUE is assigned to the output port COUNT outside the process.
This temporary signal is assigned in architecture not in process

19. IF statement observations
The last example shows the general principle of describing counters and “generalized registers”.
We operate on the entire signal COUNT_VALUE rather than on separate bits as before.
Micro-operations on the generalized register signal can be boolean, arithmetic, shift, whatever.
They treat the WHOLE name, not its bits.
This is a powerful principle to describe generalized registers, counters and other parts of data path.
Both synchronous and asynchronous micro-operations can exist.

20. Let us observe this counter’s simulation
If statement timing
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30 31
if (RSTn = '0') then
COUNT_VALUE <= 0;
elsif (CLK'event and CLK = '1') then
if (PL = '1') then
COUNT_VALUE <= DATA;
elsif (EN = '1') then
if (COUNT_VALUE = 31) then
else
COUNT_VALUE <=
COUNT_VALUE + 1;
end if; 1 2 3
Let us observe this counter’s simulation
EE514

21. If statement: result of synthesis from behavioral descriptions
Discuss synthesis from behavioral descriptions in CAD systems – dangers and troubles

22. Example of If Statement Entity
In system level descriptions of descriptions of mixed digital-analog systems we may use IF statements in a very general way
Description of charging
Example of If Statement Entity
entity NiCadCharger is
port ( Voltage , Current : in real ;
AC : in bit ;
Charged , Recharge : out bit
) ;
end entity NiCadCharger ;

23. Example of If Statement Architecture continued
Description of charging
Example of If Statement Architecture continued
architecture ChargerArch1 of NiCadCharger is
begin
Charger_A: process ( Voltage ,
Current , AC ) is
if Voltage >= 9.6 then
Charged <= ‘1’ ;
Recharge <= ‘0’ ;

24. Example If Statement continued
Description of charging
elseif ( AC = ‘1’ and Current < 0.5 )
then
Charged <= ‘0’ ;
Recharge <= ‘1’ ;
else
Recharge <= ‘0’ ;
end process Charger_A ;
end architecture ChargerArch1 ;

25. Select Conditional Statements
The Particular Value of an Expression Determines Which Statements Are Executed
The Sequential Equivalent To the Select Concurrent Conditional Assignment Statement Is The Case Statement
Two statements: CASE and WITH-SELECT
Both use WHEN, both illustrated in next two slides

26. Select Concurrent Syntax
with expression select
signal_identifier <= options
selected_waveforms ;
selected_waveforms <=
{ waveform when choices , }
waveform when choices

27. Case statement Case_statement ::= case expression is
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Case_statement ::= case expression is
when choice(s)=>
sequence of sequential statements
[when choices(s)=>
sequence of sequential statements]
end case;
EE514

28. Alternatives for “choices”
simple_expression |
discrete_range |
element_simple_name |
others )
{ | ... }

29. Case Statement
Particular Value of an Expression Determines Which Statements Are Executed

30. Choices in Case Statements
Locally Static, Determined During Analysis Phase
Exactly One Choice for Each Possible Value of Selector Expression
More Than One Choice Can Be Listed for Each “When”

31. Choices in Case Statements
Case Specification Alternatives
Enumerate specific value(s)
Discrete Range
Subtype
others
Keyword Which Precedes the Alternative to Be Used If All Other Case Alternatives Fail

32. Example of Case Statement
entity Multiplexer is
port (
MuxSelect : in subtype MuxType is
positive range 0 to 3 ;
In_0 , In_1 , In_2 , In_3 : in bit ;
MuxOut : out bit ) ;
end entity Multiplexer ;
4_to_1_MUX :
case MuxSelect is
when 0 =>
MuxOut <= In_0 ;
when 1 =>
MuxOut <= In_1 ;
when 2 =>
MuxOut <= In_2 ;
when 3 =>
MuxOut <= In_3 ;
end case 4_to_1_MUX ;

33. This example illustrates many possibilities of CASE
CASE statement
This example illustrates many possibilities of CASE

34. Example of CASE statement
End CASE_ARC;

35. Another Example of CASE statement

36. Case statement First observe how type is declared
begin
case MONTH is
when FEB =>
if LEAP then
DAYS <= 29;
else
DAYS <= 28;
end if;
when APR | JUN | SEP | NOV =>
DAYS <= 30;
when JUL to AUG =>
DAYS <= 31;
when others =>
end case;
end process;
end RTL;
package PACK is
type month_type is (JAN, FEB, MAR, APR, MAY, JUN, JUL, AUG, SEP, OCT, NOV, DEC);
end PACK;
use work.PACK.all;
entity CASESTMT is
port (
MONTH : in month_type;
LEAP : in boolean;
DAYS : out integer);
end CASESTMT;
architecture RTL of CASESTMT is
begin
p0 : process (LEAP, MONTH)
Let us observe DAYS as a function of MONTH and LEAP

37. In this example time has no meaning, this is combinational
Case statement
LEAP
In this example time has no meaning, this is combinational
MONTH

38. Null Statements
1. Need Method of Specifying When No Action Is to Be Performed, e.g., In Case Statement
[ null_label : ] null ;
2. Use As “Stub” for Code to Be Written
FlirFocus: process ( range, aperture )
begin
null ;
end process FlirFocus ;

39. Loop statement Loop_statement ::=
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Loop_statement ::=
[loop_label:][while condition|for identifier in discrete_range] loop
sequence of sequential statements
end loop [loop_label];
EE514

40. Examples of LOOP statements

41. Loop Statements Used for Repeated Execution of Sequential Statements
Alternatives
Infinite
Single or multi-phase clock
Whole system turned on

42. More Loop Statements Exit on condition Inner & Outer Loops Next While
For

43. Loop statement Example of behavioral description
loop1 : for i in 0 to 9 loop
-- notice that i is local in loop1
exit loop1 when A(i) > 20;
next when A(i) > 10;
sum := sum + A(i);
end loop loop1;
if i = 20 then
TOTAL <= -33;
else
TOTAL <= sum;
end if;
end process;
end RTL;
entity LOOPSTMT is
end LOOPSTMT;
architecture RTL of LOOPSTMT is
type arytype is array (0 to 9) of integer;
signal A : arytype := (1, 2, 3, 4, 11, 6, 7, 23, 9, 10);
signal TOTAL : integer := 0;
begin
p0 : process (A)
variable sum : integer := 0;
variable i : integer := 20;
sum := 0;
Looping identifier, not a variable
1. Observe type declaration
2. Observe that i in loop is a different i than outside because it is 20, not 9 here
3. Observe that NEXT goes to end of loop and EXIT exits the loop.
4. Observe that variable i is constant whole time
Example of behavioral description

44. Loop statement
Note:
The looping identifier i is not visible outside the loop statement, and the local variable i is not the same as the looping identifier. Variable i is used to assign the signal TOTAL.This value remains the same
begin
sum := 0;
loop1 : for i in 0 to 9 loop
exit loop1 when A(i) > 20;
next when A(i) > 10;
sum := sum + A(i);
end loop loop1;
if i = 20 then
TOTAL <= -33;
else
TOTAL <= sum;
end if;
end process;

45. Loop statement loop1 : for i in 0 to 9 loop
entity LOOPSTMT is
end LOOPSTMT;
architecture RTL of LOOPSTMT is
type arytype is array (0 to 9) of integer;
signal A : arytype := (1, 2, 3, 4, 11, 6, 7, 23, 9, 10);
signal TOTAL : integer := 0;
begin
p0 : process (A)
variable sum : integer := 0;
variable i : integer := 20;
sum := 0;
loop1 : for i in 0 to 9 loop
-- notice that i is local in loop1
exit loop1 when A(i) > 20;
next when A(i) > 10;
sum := sum + A(i);
end loop loop1;
if i = 20 then
TOTAL <= -33;
else
TOTAL <= sum;
end if;
end process;
end RTL;

46. TOTAL, SUM and i as a function of a(i)
Loop statement
TOTAL, SUM and i as a function of a(i)
Time not important, only order of events
Initial values of a(iI)
New values of a(i)
Sum is 23 because larger than 10 are skipped
Variable i always 20, as initially asigned

47. Infinite Loop Entity, e.g.,
entity 2_Phase_Clock is
port ( Clk : in bit ;
Phase_1 , Phase_2 : out bit ) ;
end entity 2_Phase_Clock ;

48. Infinite Loop Architecture, e.g.,
architecture 2PC of 2_Phase_Clock
begin
variable P1 : bit ;
loop
wait until Clk = ‘1’
if P1 = ‘0’ then
Phase_1 <= ‘0’ ;
Phase_2 <= ‘1’ ;
P1 := ‘1’ ;

49. Infinite Loop Architecture, e.g.,
else
Phase_1 <= ‘1’ ;
Phase_2 <= ‘0’ ;
P1 := ‘0’ ;
end if ;
end loop 2PC ;
end architecture 2PC ;

50. Exit on Condition, e.g., variable String_Length : positive := 0 ;
constant String_Max : positive := 80 ;
StringFill : loop
wait until Char_In ;
String_Length := String_Length + 1 ;
exit when String_Length = String_Max ;
end loop StringFill ;

51. Inner & Outer Loops for Row_Index in 1 to Row_Max Outer_Loop: loop
Inner_Loop: loop
exit Outer_Loop when Pixel_In = EOF ;
New_Image ( Row_index, Col_Index ) :=
Pixel_In ;
end loop Inner_Loop ;
end loop OuterLoop ;
error

52. While Loop, e.g.,
The Loop Only Executes, and Continues to Execute, If the Boolean Expression Evaluates to True, and Continues to Be Evaluated As True.
While String_Length <= String_Max
String1: loop
String_Length := String_Length + 1 ;
end loop String1 ;

53. For Loops
The Loop Variable Is of Type Constant and Hence It Cannot Be Modified Within the Loop
The Loop Variable Is a Strictly Local Constant

54. Error here and previous
For Loop, e.g.,
for String_Index in 1 to String_Max
String_Reverse : loop
My_String ( String_Index ) :=
Buffer ( String_Max - String_Index +1 );
end loop String_Reverse ;
Error here and previous

55. Next statement Jumps to the end of the loop, but next repeats the loop
SYNTAX:
Next_statement ::= next [loop_label][when condition ];
Jumps to the end of the loop, but next repeats the loop
Must be enclosed by a loop statement with the same loop label.
The next statement applies to that loop statement.
If the loop label is not specified, it always applies to the innermost level of the loop statements.

56. Examples of NEXT statement
In general good to have many labels to document program well

57. Next Loops
The Next Statement Terminates Execution of the Current Iteration and Starts the Subsequent Iteration
If There Is a Loop Label the Statement Applies to That Loop
If There Is No Loop Label, the Statement Applies to the Inner-Most Enclosing Loop

58. Next Loop, e.g., loop_1: loop loop_2: loop something ;
next loop_1 when String_Length = 0 ;
more_something ;
end loop loop_2 ;
end loop loop_1 ;

59. Exit_statement ::= exit [loop_label][when condition];
Must be enclosed by a loop statement with the same loop label.
The exit applies to that loop statement.
If the loop label is not specified, the exit always applies to the innermost level of the loop statements.

60. Example of EXIT statement
Next jumps before end of loop, exit jumps out of loop

61. Exit statement constant TABLE : matrix := entity EXITSTMT is
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entity EXITSTMT is
end EXITSTMT;
architecture BEH of EXITSTMT is
type matrix is array (1 to 5, 1 to 4) of integer;
constant TABLE : matrix :=
( (1, 2, 3, 4),
(2, 8, 1, 0),
(8, 5, 3, 7),
(3, 0, 2, 1),
(1, 1, 0, 2) );
begin
p0 : process
variable NUMROW, ROWSUM : integer := 0;
variable ROWDONE, ALLDONE : bit;
begin
ALLDONE := '0';
outloop : for i in matrix'range(1) loop
ROWSUM := 0;
ROWDONE := '0';
inloop : for j in matrix'range(2) loop
ROWSUM := ROWSUM + TABLE (i, j);
if (ROWSUM > 10) then
NUMROW := NUMROW + 1;
exit outloop when NUMROW = 2;
exit; -- get out of inloop
end if;
wait for 20 ns;
end loop inloop;
Change after 20ns
EE514

62. Set to one after every row is done
Exit statement
12/3/2018
ROWDONE := '1';
wait for 20 ns;
end loop outloop;
ALLDONE := '1';
wait for 60 ns;
end process;
end BEH;
Set to one after every row is done
Lasts for 20ns
EE514

63. constant TABLE : matrix :=
entity EXITSTMT is
end EXITSTMT;
architecture BEH of EXITSTMT is
type matrix is array (1 to 5, 1 to 4) of integer;
constant TABLE : matrix :=
( (1, 2, 3, 4),
(2, 8, 1, 0),
(8, 5, 3, 7),
(3, 0, 2, 1),
(1, 1, 0, 2) );
begin
p0 : process
variable NUMROW, ROWSUM :
integer := 0;
12/3/2018
variable ROWDONE, ALLDONE : bit;
begin
ALLDONE := '0';
outloop : for i in matrix'range(1) loop
ROWSUM := 0;
ROWDONE := '0';
inloop : for j in matrix'range(2) loop
ROWSUM := ROWSUM + TABLE (i, j);
if (ROWSUM > 10) then
NUMROW := NUMROW + 1;
exit outloop when NUMROW = 2;
exit; -- get out of inloop
end if;
wait for 20 ns;
end loop inloop;
ROWDONE := '1';
wait for 20 ns;
end loop outloop;
ALLDONE := '1';
wait for 60 ns;
end process;
end BEH;
=10
NUMROW
ROWDONE
EE514

64. More on Assertion Statements
Assertion Statements Check Expected Conditions at Their Location in the Program.
Assertion Statements Are Not “If” Statements Since They Test for the Correct, Expected Results Rather Than an Error.

65. Assertion & Report Statements
If Other Than the Expected Condition, the Report and Severity Expressions Are Executed
[ assertion_label : ] assert Boolean_expression
[ report expression ]
[ severity expression ] ;

66. Assertion Statements Expression Must Evaluate to String
If Other Than the Expected Condition, the Report and Severity Expressions Are Executed

67. Uses of Assertion Statements
Simulation
notify user when statement is executed
optionally print report expression
optionally print severity e.g., (note, warning, error, failure)
determine whether to continue

68. Uses of Assertion Statements
Synthesis
Value in assertion statement is assumed and circuit optimized on that value
Verification
Determine that the assertation statement is true for all possible values based on all possible routes to the statement

69. ASSERT statement

70. Example of ASSERT statement

71. Report Statement [ report_label : ] report expression
[ severity_expression ] ;

72. Report Statement A Note Is Printed Whenever the Expression Occurs
Report Always Produces a Message
Useful for Tracing Values or Paths During Execution
Expression Must Evaluate to String
[ report_label : ] report expression
[ severity expression ] ;

73. Aliases

74. Aliases

75. HW 2-11 LIBRARY ieee ; USE ieee.std_logic_1164.all ;
PACKAGE Clock_2_11_pkg IS
COMPONENT Clock_2_11
--GENERIC ( ) ;
PORT ( ClockOut : out bit := '0' );
END COMPONENT ;
END Clock_2_11_pkg ;

76. HW 2-11 ENTITY Clock_2_11 IS -- GENERIC ( );
PORT ( ClockOut : out bit := '0' );
END Clock_2_11 ;

77. HW 2-11 ARCHITECTURE KJH_Clock OF Clock_2_11 IS BEGIN
clock_gen : PROCESS
ClockOut <= '1'; WAIT FOR 10 ns ;
Clockout <= '0'; WAIT FOR 10 ns ;
END PROCESS clock_gen ;
END KJH_Clock ;

79. Sources Prof. Krzysztof Kuchcinski
VLSI, Ohio University, Prof. Starzyk
Professor K.J. Hintz.
California State University Northridge