1. USCMS HCAL FERU: Front End Readout Unit
Drew Baden
University of Maryland
February 2000

2. HCAL Front-End Readout Unit
Joint effort between:
University of Maryland – Drew Baden (Level 3 Manager)
Boston University – Eric Hazen, Larry Sulak
University of Illinois, Chicago – Mark Adams, Rob Martin, Nikos Varelas
Web site:
Has latest project, spreedsheets, conceptual design report, etc…
This talk
Overview
Status
Cost and Schedule
CMS-TriDAS. 3-Dec-18

3. Parameters QIE Readout
2 Channels per fiber, 7 data bits + 2 cap bits per channel
HP G-links, 20 bit frames, 16 bits data
HCAL Channels (includes calibration fibers) – drives the cost
Towers Fibers Trig Towers
BARREL 4,824 2, ,412
OUTER 2,280 1,
ENDCAP 3,672 1, ,836
FORWARD ,556 1, (approximation)
TOTAL , , ,148
Trigger Primitives
Need to understand 53° Overlap region, high rad region, etc.
Data rates estimated using 15% occupancy at L=1034
Assume 100kHz Level 1 accepts
Method for Level 1 trigger crossing determination under study (Eno etal.)
CMS-TriDAS. 3-Dec-18

4. Readout Crate Components
HCAL Readout Crate
Standard 9U VIPA
P3 backplanes not anticipated (saves $)
18 HCAL Trigger and Readout Cards (HTR)
Raw data fiber input
16 fibers, 2 channels per fiber=32 channels per card
Level 1 Trigger Primitives output
Level 2 Data output to DCC
1 Data Concentrator Card (DCC)
Buffers 100 L1 accepts for DAQ
Also serve as DDU?
1 HCAL Readout Control Module (HRC)
VME
CPU for fast and slow monitoring
TTC fanout
1 Gbps fibers
(2 channels/fiber)
18 HTR Cards H R C D T
Front End: QIE Tx
To: DAQ FED
Level 1 Trigger
Level 1 Trigger Data
Vitesse, Copper Link,
20m cables, 1 Gbps
Level 2 Raw Data
200 Mbps link
CMS-TriDAS. 3-Dec-18

5. HCAL TRIGGER and READOUT Card
Raw data Inputs on front panel:
16 digital serial fibers from QIE
1 serial twisted pair with TTC information
Level 1 Trigger Tower data outputs on rear connector:
8 twisted pair
Investigating use of quad pair cable works
Would allow use of 2 or 4 RJ45 connectors
Might be able to do that on front panel as well
DAQ data output to DCC on front panel:
Single connector running LVDS
Level 1 Path:
Trigger primitive preparation
Transmission to Level 1
Level 2/DAQ Path:
Buffering for Level 1 Decision
No filtering or crossing determination necessary
Transmission to DCC for Level 2/DAQ readout
CMS-TriDAS. 3-Dec-18

6. HTR Card Conceptual Design
Current R&D design focusing on
Understanding HCAL requirements
Interface with FNAL group
Minimizing internal data movement
Using large FPGA vs ASICS
Pretty much a given that we will not use the ASICs from “FERMI”
No card-to-card communication
Has implications with respect to summing in 53° region, and fiber routing
How to implement I/O
R&D on all relevant links is in progress
Reducing costs
On-chip FPGA memory is a big factor
Eliminating P3 backplane saves ~$1000/card and $1500/crate
Investigating use of Vitesse receivers for HP optical-to-electrical parts
CMS-TriDAS. 3-Dec-18

7. Data Concentrator Card
Preliminary design….
TTCRx
PC-MIP cards for data input
18 HTR cards
3 inputs x 6 cards = 18 inputs
PMC cards for Level 2/DAQ buffering and etc.
DDU
Processing FPGA
Dual Port Memory
Protocol FPGA
FMU
RUI Link Tx
Build motherboard to accommodate
PCI interfaces
VME interface
CMS-TriDAS. 3-Dec-18

8. Hcal Readout Control Module
9U motherboard (some similarities to DCC – maybe end up being same….TBD)
Functionality:
TTC fanout
TTCRx daughter card
18 outputs on front panel – probably use small footprint connectors
Input from DCC
To be determined
Used for monitoring, and possibly VME data path
Fast Monitoring Unit
Implemented on PMC daughter board
Will most likely contain FPGA implementation
Slower Monitoring and crate communication
PMC CPU, buy from industry
Busy signal output
To go to HCAL DAQ Concentrator (HDC)
Demonstrator implemented piecemeal
Industry CPU card
Separate 6U TTC fanout card
Motherboard and PMC daughter board R&D
CMS-TriDAS. 3-Dec-18

9. Project Status HTR: DCC HRC Overall integration
R&D on I/O cards underway at UMD
LPD ASIC vs. FPGA discussions are progressing
Xilinx VERTEX-E technical data and cost estimates underway
Altera APEX chips under study – have a 20k400 free sample to play with
LPD specs sent to us by CAEN
We will evaluate our requirements, perhaps work with CAEN on how to implement in FPGA
Better understanding of derandomizing buffers
Discreet simulation indicates L1A max per orbit greatly minimizes buffer sizes
Will make FPGA implementation more cost effective
DCC
R&D on DCC motherboard underway at BU
HRC
UIC ramping up to provide some functionality of HRC card by fall 2000
Overall integration
Synchronization issues under consideration
We are being educated
HCAL and ECAL group are in better contact about how to deal with these issues
Efforts underway to bring Mr. daSilva (ECAL DCC designer) to USA this summer
Plans to use early production cards for Alcove tests in early 2003
CMS-TriDAS. 3-Dec-18

10. Project Progression Demonstrators 1st Prototype 2nd Prototype
Limited scope
1st priority: functional test of requirements
2nd priority: hardware implementation
Integration: fall of 2000
1st Prototype
Hardware implementation is a priority
Full channel count
Integration: fall of 2001
2nd Prototype
Final cards
Production will be clones of these
No big integration effort necessary
Completed: summer 2002
Production
Begins: fall 2002
Duration: 4-6 months, all cards ready by spring 2003
CMS-TriDAS. 3-Dec-18

11. Current Issues Parts cost
HTR implementation in 4 FPGA in 463 cards = 1852 FPGAs
Trying to pin down Xilinx and Altera
Still learning about functional requirements, e.g.
how to design with uncertain crossing determination algorithm in HTR
How DDC interfaces with DAQ
Synchronization
daSilva will help a great deal with making this more concrete
Might have design implications, but not at demonstrator stage
FPGA programming
Need to do this at the simulation level – logic block design is insufficient
This is our biggest engineering concern, and we are doing the following:
Gain expertise in-house:
Asked Altera for cost estimate for a course at UMD (4-5 engineers, me, grad student)
They said they’d help us with the design of the HTR FPGA code
Mining expertise within the Masters level EE students.
CMS-TriDAS. 3-Dec-18

12. Timeline
CMS-TriDAS. 3-Dec-18

13. Project Costs (estimated uncertainty 10%)
Item
Cost
Effort:
Engineering
$926,678
Technician
$140,759
Total
$1,067,437
M&S:
Prototyping
$ 233,100
Production
$2,094,632
$2,327,732
Travel:
$45,000
Grand Total
$3,440,169
CMS-TriDAS. 3-Dec-18