1. Department of Electronic Engineering
VLSI Technology
Don-Gey Liu, Prof.
Department of Electronic Engineering
Feng Chia University
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2. Introduction Industries Development Fabrication Technology IC Families
VLSI Technology 2003
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Introduction
Industries
Development
Fabrication Technology
IC Families
Self-Aligned CMOS Process Flow
Layout Design
Roles of Computer
Fabrication Equipment
References
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3. Industries
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4. Industries
Jobs and Facilities
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5. Industries
Technologies
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6. Development Integrated Circuits and profiles 2018/12/3
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7. Development The 1st IC 2 Tx A few million Tx/Chip 2018/12/3
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8. Development
The trends
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9. Development The state-of-the-art technology 1 nm 2018/12/3
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10. Development
The 1st Transistor
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11. Development Grow junction transistor technology 2018/12/3
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12. Development
Alloy junction technology
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13. Development Double diffused mesa transistor technology Contact
1st diffusion
Mesa etch
2nd diffusion
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14. Development Planar process by Jean Hoerni of Fairchild
Photolithography
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15. Fabrication Technology
Photolithography Process
Repeated transferring patterns 底片 相紙
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16. Fabrication Technology
Process Flow – To construct 3D structures by planar (2D) techniques
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17. Fabrication Technology
Process Integration – Integrated planar thin-film technology
Film deposition/growth
PVD/CVD/Deposition
Oxidation/Nitridation
Impurity doping
Photolithography
Exposure/Development/Rinse
Etching
Wet etching/Dry etching
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18. Fabrication Technology
Integration on substrates
Isolation
Metallization
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19. Fabrication Technology
Modern CMOS IC
SPTM(1P3M) M3
Via M2 P1 M1
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20. Fabrication Technology
Modern COMS IC
SPPM(1P5M) M5 M4 M3
Via2 M2 M1
Via1 P1
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21. Fabrication Technology
Modern CMOS IC
State-of-the-art Technology1
Cu technology
1 A. S. Brown, “Fast films [IC interconnect insulation], IEEE Spectrum , Vol. 40(2) , pp , Feb 2003.
M1/P1
Channel M2 M3 M4 M5 M6 M7 M8 M9
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22. Fabrication Technology
Cu Technology
1. Dielectrics formation
Si Sub
Underlying layers
Spin-On / CVD Oxide
3. Etching
Si Sub
Underlying layers PR OX
4. Cu plating
Si Sub
Underlying layers PR OX
2. Photo-lithogrophy
Si Sub
Underlying layers PR
Spin-On / CVD Oxide
5. Removal
Si Sub
Underlying layers OX
Si Sub
Underlying layers
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23. IC Families
Bipolar IC
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24. IC Families
NMOS IC
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25. IC Families
CMOS IC
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26. Self-Aligned Process Flow
LOCOS
Chanstop
VTH tuning
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27. Wafer in M1 PR
Si3N4
SiO2
Substrate
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28. LOCOS isolation Active Area Bird’s beak Chanstop AA FOX B IMP
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29. Trench isolation Compact Active Area Dry etching CMP AA SiO2 CVD
Oxidation
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30. Wells M3 M2 Phosphorus Implantation Boron Implantation 2018/12/3
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31. Gate VTH tuning M5 M4 Arsenic Implantation Boron Implantation
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32. Gate M6 P1
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33. LDD extension SiO2 CVD Etch Back M8 M7 Boron Implantation
Arsenic Implantation
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34. Source/Drain ElectrodesM9
M10
Boron Implantation
Arsenic Implantation
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35. Contact/M1 TiN removal Etch Back M11 SiO2 CVD CMP TiSi2/TiN Formation
Ti Sputtering
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36. VIA1
M12
W CVD
CMP
Etching
TiN Sputtering
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37. M2
M13
SiO2 CVD
Plasma Etching
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38. VIA2
M12
CMP
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39. M2/Passivation Al sputtering Plasma etching SiO2 deposition
Si3N4 Deposition
SiO2 Deposition
M13
Al sputtering
Plasma etching
SiO2 deposition
Si3N4 deposition
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40. Layout design – Schematics
INV
NOR
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41. Layout Design – INV and NOR
VDD
VSS A
OUT B
VDD
VSS IN
OUT
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42. Devices on Wafer
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43. Logic Gates Layout - INV
VDD
VSS IN
OUT
VDD
VSS IN
OUT
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44. Logic Gates Layout – NOR
VDD
VSS A
OUT B
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45. Role of Computer Technology CAD Virtual Fab / Fabless development
Finding potential problems before fabrication
Reducing developing time/costs
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46. Fabrication Equipment
Crystal Growth
Wafer Preparation
Clean room
Cleaning station
Wafer carrier
Pattern transferring
Heat treatments
Measurement
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47. Crystal Growth
Vertical
Horizontal
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48. Crystal Growth
Czochralski method
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49. Crystal growth
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50. Crystal Growth
Floating-zone method
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51. Crystal Growth
Ingot
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52. Wafer Preparation
Cutting
Shaping
Polishing
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53. Clean room
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54. Clean Room
Factory
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55. Clean Room
Factory
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56. Clean Room
Garments
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57. Clean Room
Production line
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58. Clean room
Testing room
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59. Cleaning Station
Wet bench
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60. Wafer Carrier
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61. Pattern Transferring Layout stream out Mask fabrication Transferring
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62. Pattern Transferring Resist inspection After Develop Inspection (ADI)
Cross sectional view Top view
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63. Pattern Transferring Step and scan system Stepper 2018/12/3
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64. Heat Treaments – Oxidation
Furnace O2
H2O
H2 + O2
HCl or TCA
A cleaner
RTO
Real temperature is unknown
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65. Heat Treatments Diffusion Rapid Thermal Annealing 2018/12/3
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66. Measurement
Electron microscopy
SiO2 Si
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67. References Fabrication Technology Vacuum Technology
J. D. Plummer, M. D. deal, P.B. Griffin, “Silicon VLSI Technology – Funfamentals, Practice and Modeling,” Prentice Hall Inc., 2000(高立出版社).
S. M. Sze, “VLSI Technology,” McGraw-Hill Book co., 1988(新月圖書公司).
S. M. Sze, “Semiconductor Devices – Physics and Technology,” Bell Telephone Laboratories, Inc., 1985(中央圖書出版社).
Vacuum Technology
呂登復,”實用真空技術,” 新竹黎明書店.
Measurement Technology
D. K. Schroder, “Semiconductor Material and Device Characterization,” John Wiley & Sons, Inc., 1990(臺北圖書公司).
Journals
Electronic Devices Society, IEEE
IEEE Trans. Electron. Dev.
IEEE Electron. Dev. Lett.
Internat’l Electron. Dev. & Mater. (IEDM) Conference
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