1. CPU: software architecture

2. INSTRUCTION SET (PART 1)
General Introduction
INSTRUCTION SET (PART 1)

3. General Introduction (1/5): On Instructions
Instruction operate with data or with the flow of the program
The following information is absolutely needed to define an instruction:
OpCode: What is the operation to be done
Operands: What operands are involved
Addressing mode: Where is data to be found
Additional information may include size of operands or other modifiers.

4. General Introduction (2/5): On instructions
The number and type of instructions, i.e., what they do, depend on the MCU or MPU family and model.
Several types of instructions are found in almost any MCU or MPU
Syntax may be different
An instruction set is not necessarily independent
It may happen that the operation of one instruction may be realized with other with proper operands.

5. General Introduction (3/5): On operands
The maximum number of operands of instructions depends on MCU or MPU model
Most small microcontrollers work with two operands.
Some specific families work with three operands
In many instances, one or more operands may be implicit
Two operands (data) are considered: destination and source

6. General Introduction (4/5): Destination
The result of an instruction, except for some cases, is stored either as a
CPU register content
memory cell (or cells, depending on data size) contents
contents of register of an IO device.
The place where the result is stored is called destination (dest)

7. General Introduction (5/5): Source
The source is the other operand involved in the operation
It may be a
Constant data or a
CPU Register, memory cell(s) or IO register contents
Abusing of language, source is referred to as
The source itself alone
An expression that involves the source and destination (as in source + destination)
An expression that includes the source and other information

8. Register Transfer Notation (RTN)
The register transfer notation (RTN) is a symbolic, MCU independent notation to indicate CPU transactions, operations in programs, etc. Arrow points to destination:
dest  src
In an expression such as dest  dest + source, the destination data in “dest + source” is the one previous to the transaction, and “dest” on the left is the data after transaction
PC  NewAddress is mentioned as “Jump to NewAddress” or “ GOTO Newaddress”

9. Hybrid RTN and convention (1/3)
Convention: When RTN is too complicated, a simple sentence is preferred
Jump to address, instead a PC  address
Operands are denoted as follows:
For a CPU register, the register name is given .
In MSP430: R4, R5, etc.
INTEL 8086: AX, AH, BL, etc.
In general, simply register Reg X, or RX
A constant data by the number or #number
Example R6  34h, or R6 #34h means R6 is stored with number 34h

10. Hybrid RTN and convention (2/3)
When data is to be stored in memory, or IO device register, the address at memory is provided in parenthesis or preceded by &.
(2030h) denotes data at address 2030h
(Hello) denotes data at address defined by a label named Hello .
(R5) denotes data at address given by contents of register R5
(R5 + X) denotes data at address given by the result of adding X to the contents of register

11. RTN Conventions (3/3)
Data to register pertaining an I/O subsystem device: same notation as in memory, except that address belong to the Device register, and it must be indicated. Usually, use the name of the register
(P1OUT) denotes the address of Output Register of Port 1
(WDTCTL) denotes the address of the Watchdog Timer Control Register
Addresses are also denoted with & (loan from C)
(2030h) same as &2030h
(P1OUT) same as &P1OUT

12. Machine Language
Machine language instruction is the set of n-bit words that define an instruction
If there are more than one word, the first in the set is called instruction word
The instruction word contains:
OpCode: field of bits that define the operation
Destination and Source bit fields
Addressing Mode field: That define how and where to read data, destination and source fields.

13. Example: MSP430 instructions

14. From machine to assembly (1/2)
Assembly language makes programming “in machine language” much easier and direct
Each machine language instruction is associated to one and only one assembly language instruction
Converting an assembly language to its machine language version is “to assemble” .
The software tools to assemble are
assembler : works all instructions before assembling
Interpreter or line interpreter : works with an isolated instruction
“To disassemble” is to translate the machine instruction into assembly instruction

15. Example Opcode Name: add Operand size: word add.w datum
Source info: immediate add.w #
480d
Destination Register mode: add.w #480Dh,R13

16. From machine to assembly (2/2)
An assembly language instruction consists of
A mnemonics: Name given to the opcode,
Operands written in a specific syntax for addressing mode
The specific syntax for mnemonics, operands and order in the instruction is CPU family dependent.
The three examples below all express an instruction of the form dest  (0204h), dest is a CPU register and the data size is a byte
MSP mov.b h, R6 (CPU register is R6)
Intel mov AH, [0204h] (CPU register is AH)
M68CH11 LDAA $0204 (CPU register is accumulator A)

17. Instruction set (Part 2)
Instruction Types
Instruction set (Part 2)

18. Instruction Types (1/2) Data transfer instructions (dest  src)
For reading and writing to and from memory and IO registers, Storing with data, copy from registers.
These instructions in general do not affect flags
Arithmetic and logic operations
Of the type dest dest * src (* means an operation), with flags being or not affected
Of the type (dest*src), affecting only flags

19. Instruction Types (2/2) Register operations: manipulates bit order
Shift, roll and rotation
Flow program operations: On execution, they modify the content of the PC register
Jump instructions (PC  New Address)
Subroutine instructions:
Call and Return
Interrupt instructions:
Return from Interrupt.

20. Transfer operations (1/2)
Move instructions: copy source data onto destination data (dest src)
MSP430 mnemonics mov, mov.w, mov.b
Also called “load”, “store” instructions
Input and output transfer instructions
For those MCU with IO mapped IO systems
Input*: dest  (Input Port)
Output*: (Output port)  Source

21. Common Data Transfer Instructions
Stack transfer operations, managed by SP register (explained later)
Push: (TOS) src
Pop or Pull: dest  (TOS)
TOS means Top Of Stack
Swap: dest  source (exchange of contents; both operands are erased and reloaded)

22. Arithmetic instructions (1/2) Addition and Subtraction
Addition Operations:
Addition: dest  dest + src
Addition with carry: dest  dest + src + CFlag
Subtraction Operations: Usually with two’s complement addition
Subtraction: dest  dest – src
Subtraction with borrow :
dest  dest – src – BF for dual Carry/Borrow cases
dest  dest + NOT(src) + CF, when CF=0 denotes borrow
Compare operation: dest – src; only flags affected

23. Arithmetic instructions (2/2) Multiplication and division
Not all microcontrollers’ ALU’s implement these operations.
Operands and destination sizes are of outmost importance.
When not supported, these operations are done by software
Special cases are dedicated peripherals.

24. Logic Instructions General introduction
Bitwise and not bitwise
Most microcontrollers support only bitwise logic operations
Non bitwise logic operation principles:
Yield a boolean result (usually in a flag)
In source, “1” means operand is not zero; “0” means operand is zero
Used mainly in high performance systems or as part of “high level” instructions

25. Bitwise Logic Operations (1)
dest  dest*source means dest(j)dest(j)*source(j)
Bitwise operations permit individual bit manipulations
The source is usually called “mask”
“1”s in mask indicate which bits are to be affected
AND: dest  dest .AND. src
OR: dest  dest .OR. src
XOR: dest  dest .XOR. Src
NOT: dest  NOT(dest)

26. Bit manipulation : CLEAR
0.AND.X=0;
1.AND.X=X
To clear specific bits in destination, the binary expression of the source
has 0 at the bit positions to clear and 1 elsewhere
Instruction in MSP430:
BIC.B # b,R6 R6

27. Bit manipulation : CLEAR
0.AND.X=0;
1.AND.X=X
To clear specific bits in destination, the binary expression of the source
has 0 at the bit positions to clear and 1 elsewhere
Instruction in MSP430:
AND.B # b,R6 R6

28. Bit manipulation : TEST
0.AND.X=0;
1.AND.X=X
To clear specific bits in destination, the binary expression of the source
has 0 at the bit positions to clear and 1 elsewhere
Instruction in MSP430:
BIT.B # b,R6 R6

29. Bit manipulation : SET
To set specific bits in destination, the binary expression of the source
has 1 at the bit positions to set and 0 elsewhere
0.OR.X=X;
1.OR.X=1
MSP430: BIS.B # b,R6

30. Bit manipulation : TOGGLE
To toggle specific bits in destination, the binary expression of the source
has 1 at the bit positions to invert and 0 elsewhere
0.XOR.X=X;
1.XOR.X=X’
MSP430: XOR.B # b,R6 XOR.B #68,R6
REG R6

31. Register operations: Shifts, rolls and rotates
Shift (or roll) right logically:
0 dest(N-1)dest(N-2)  ….  dest(1)  dest(0)  CF
Shift left:
C dest(N-1)  dest(N-2)  ….  dest(1)  dest(0)  0
Shift (or roll) right arithmetically:
Dest(N-1) dest(N-1)dest(N-2)  ….  dest(1)  dest(0)  CF
Rotate right through:
CFold dest(N-1)dest(N-2)  ….  dest(1)  dest(0)  CF

32. Shift and rotate examples
Carry Old
Carry X 1
Original
Shift right logically
Shift right arithmetically
Shift left A
Shift left with carry
rotate right through carry

33. Program Flow Instructions (1) Jumps or Branch --
ACTION: PC  NewAddress
Unconditional jumps: (jmp)
GOTO!!!!!!!!!!! Ohhhhhhh!!!!!!
Conditional jumps: test a flag condition
Basic tools for decisions

34. Conditional jumps (simple flags)
Jump if zero (jz)
Z=1
Jump if not zero (jnz)
Z=0
Jump if carry (jc)
C=1
Jump if not carry (jnc)
C=0
Jump if negative (jn)
N=1
Jump if not negative (jp)
N=0
Jump if overflow (jv)
V=1
Jump if not overflow (jnv)
V=0

35. Example 1: Delay loop

36. Example 2: Repeat process N times
Counter  N
Label: Do process
counter  counter -1
Jump if not zero to Label

37. Examples of composed Conditional Structures using basic structure
Single Flag(s) condition
Instruction affecting flags
FLAG?
Yes No
Multiple Flags:
FLAG_A AND FLAG_B
Multiple Flags:
FLAG_A OR FLAG_B
Instruction affecting flags
FLAG_A?
Yes No
FLAG_B?
Instruction affecting flags
FLAG_A?
Yes No
FLAG_B?

38. Drawing for “low level”: If sentence (1)
Inst. affecting flags
A true? NO
Yes
Block B
(NO forces jump)

39. Other names and otherConditional jumps
To be used after a compare operation A-B, for numeric decisions)
Conditional jump
Condition
Note
Jump if equal (je) (= Jump if zero)
Z=1
Jump if not equal (jne) (= Jump if not zero)
Z=0
Jump if larger or equal (= Jump if carry)
C=1
Unsigned numbers
Jump if lower (= Jump if not carry)
C=0
Jump if greater or equal (jge)
N=V
Signed numbers
Jump if less
N~=V
Other combinations available …..

40. Remarks on jumps A jump is also called a “branch instruction”
Unconditional jumps are present in almost any CPU
Not all conditional jumps are necessarily present in the CPU architecture
The use of jumps is indispensable to devise non sequencial programs.

41. Subroutines and Procedures
Subroutines (also called functions or procedures) are pieces of executable code written and stored apart from the main code
They are to be executed when invoked from main code or other subroutine, but flow must return to original “normal” flow
The Address of first instruction is called Entry Address

42. Subroutine Instructions:
Call instruction: Saves the present value of the PC register and then loads the PC with the entry address of the subroutine
a) (TOS)  PC
PC  Sub. Entry Address
Return instruction: Retrieves the address following the call in the main code [PC  (TOS)]
Important note: Subroutine programming must ensure that return is well done

43. Subroutine process Just before CALL execution PC points to next memory
location after CALL.
Upon execution, the content
of PC is pushed onto stack,
and PC loaded with address
of subroutine entry line
3. Subroutine is executed until
instruction RET (return) is
found.
4. Execution of RET pops PC,
restoring the address of the
instruction just after CALL
--- This happens every time
CALL is executed
Important remark: Subroutine must be
designed so that when RET is encountered
SP is pointing to the right location

45. Call and Return E420 Return --- - Inst Bla bla F24A Next Instr. E402
F248
CALL SUB
Entry
Addr
E400
Entry line
Before Fetch of call:
PC = F248
First step of execution:
PC = F24A, (TOS) = F24A
After return:
PC = F24A
After decode of call, and
before execute phase:
PC = F24A
Second Step of Execution
PC = E400 (TOS) = F24A

46. STACK and Stack Pointer

47. Stack Definition and Characteristics
Stack is a specialized memory segment which works in LIFO (Last In-First Out) mode. Managed by the Stack Pointer Register (SP)
Hardwired stack: physically defined, cannot change
Software defined: First address in stack defined by initialization of SP (by user or by compiler)
Stack Operations:
PUSH: storing a new data at the next available location
POP or PULL: retrieving last data available from the sequence (to be stored in some destination)
Important Note: A retrieved data is not deleted, but cannot be retrieved again with a stack operation
Top of Stack (TOS): memory address used in the stack operation (different for push or pop)

48. Basics of stack operation
Empty at start
(Only garbagge)
X x x x x x x x x x
Push TOS

49. Basics of stack operation
PUSH
(garbage not shown) D0
Pop TOS
Push TOS

50. Basics of stack operation
PUSH D0 D1
Pop TOS
Push TOS

51. Basics of stack operation
PUSH D0 D1 D2
Pop TOS
Push TOS

52. Basics of stack operation
POP D0 D1 D2
Pop TOS
Push TOS

53. Basics of stack operation
PUSH D0 D1 D3
Pop TOS
Push TOS

54. Basics of stack operation
POP D0 D1 D3
Pop TOS
Push TOS

55. Basics of stack operation
POP D0 D1 D3
Pop TOS
Push TOS

56. Software Defined Stack Grows Downwards
xxxx
xxxx-N
xxxx-2N
xxxx-3N
xxxx-4N
Push TOS
xxxx
xxxx-N
xxxx-2N
xxxx-3N
xxxx-4N D0
Push TOS
PopTOS
xxxx
xxxx-N
xxxx-2N
xxxx-3N
xxxx-4N D0
Push TOS
PopTOS D1
After a push
Empty
After a push
xxxx
xxxx-N
xxxx-2N
xxxx-3N
xxxx-4N D0
Push TOS
PopTOS D1 D2
After a push
xxxx
xxxx-N
xxxx-2N
xxxx-3N
xxxx-4N D0
Push TOS
PopTOS D1 D2
After a pop
xxxx
xxxx-N
xxxx-2N
xxxx-3N
xxxx-4N D0
Push TOS
PopTOS D1 D3
After a push

57. Stack and Stack Pointer
The Stack Pointer contents is an address associated to the stack operation
The contents of SP is sometimes called Top-of-Stack
Since contents is unique, and two addresses are associated to the TOS, there are 2 possibilities:
SP contains the PUSH-TOS (Example: Freescale)
SP contains the POP TOS (Example: MSP430)

58. SP points to PUSH TOS To do a PUSH: To do a POP:
1. Store (SP)  Data
2. Update SP  SP - N
To do a POP:
1. Update SPSP+N
2. Retrieve Dest(SP)
These steps are done automatically by CPU. D0
Push TOS
PopTOS D1 D2
(SP)
(SP+N)

59. SP points to POP TOS To do a PUSH: To do a POP:
1. Update SP  SP -N
2. Store (SP)  Data
To do a POP:
1. Retrieve Dest(SP)
2. Update SPSP+N
These steps are done automatically by CPU. D0 D1
(SP) D2
PopTOS
(SP-N)
Push TOS

60. Stack Pointer in MSP430 SP is register R1
It is always even, since the least significant bit is hardwired to 0
There is an error if user tries to load an odd number onto SP
It points to the ‘last pushed item’ (first to pop)
N=2: That is, update is always +- 2.
If pushing a byte, the msb of the word contains garbagge.

61. Important Remarks
Without any reference to the actual meaning of SP contents, and the fact that the address for pushing and pulling are different, the following conventions are generally adopted:
Contents of SP is called TOP-OF-STACK (TOS)
PUSH operation is denoted as (TOS)  source
POP or PULL operation is denoted as dest  (TOS)
You should be aware of differences!!

62. Addressing Modes

63. General introduction(1/2)
Addressing mode is the way to denote where to find (or store) the datum used in an operation
A datum or result to store can be referred to
explicitely (immediate mode)
as contents of a CPU register (register mode)
By the address of the memory or IO register(s) where it is to be found

64. General introduction (2/2)
Actual addressing modes and mode names in a family or model should be consulted in data sheet or user guide
Cases presented here are common, names may differ
Syntax depends on family system
Note: we use msp430 syntax for examples.
Specific restrictions for use is also family dependent
Orthogonal system: it accepts all registers and addressing modes in both source and destination
Except immediate mode, not valid for destination

65. WARNING
We use material from chapter 4 to introduce concepts and examples. This material will be identified during class.

66. Immediate and register modes (1/2)
Immediate mode is when datum is explicitly given
It is valid only for source
Syntax in MSP #Datum (#N)
Register mode is when datum is the contents of a CPU register
Syntax in MSP430 (and almost all MCU): Register Name Rn.

67. Immediate and Register Modes (2/2) Examples for MSP430
INSTRUCTION mov: mov src, dest stands for destsrc
Instruction does not modify source
Examples: (Register contents in hex notation)
If R5=245A, then after execution of instruction mov #0x2AC, R5  R5 = 02AC
If R5=245A, then after execution of instruction mov #-20285, R5  R5 = B0C3
If R5 = 245A and R6 = ABCD, then after execution of instruction mov R5, R6  R5 = 245A, R6=245A
mov R5,#435 is not valid!

68. MSP430: Byte instructions in register mode
As a destination, the register clears the most significant byte
As a source, only the least signifcant byte is considered:
If R5 = 245A and R6 = ABCD, then after execution of instruction mov.b R5, R6  R6 = 005A, R5=245A
If R5=245A, then after execution of instruction mov.b #0xAC, R5  R5 = 00AC

69. Memory related addressing modes (1): Direct mode
Direct mode (or absolute mode): address is explicitely given
RTN notation (X), where X is a number
(2340h)  # 654Ah means “store the word number 654Ah in memory at address 2340h”
Byte(2340h)  #0x92h+ (2340h) means “add 92h to the byte stored at address 2340h)
MSP430 variants:
Absolute mode X: mov 2340h, R6; add.b R6, 2340h
Symbolic Mode &X: mov &2340h, R6; add.b R6, &2340h
If you define jaja EQU 0x2340, mov &jaja,R6

70. Memory related addressing modes (2): Register indirect (or indirect)
Register indirect (or indirect): address is given as contents of a CPU register
RTN notation (Reg), where Reg is a CPU register
If R6=2340h, (R6)  # 654Ah means “store the word number 654Ah in memory at address given by R6, that is, 2340h”
Byte(R6)  #0x92h + (R6) means “add 92h to the byte stored at address 2340h)
MSP430 Notation @Rn, Not valid for destination:
If R5 = 2340h and [2340h]=ABCD: mov @R5, R6 yields R6 =ABCD
add.b is not valid

71. MSP430 specific: indirect with auto increment @Rn+
@Rn+ points to data at address given by Rn, but execution of instruction ALSO increments Rn by 2 for words, by 1 for bytes
Example, let [0240h]= ABCD
If R5=0240h, then after execution of  R6 = ABCD, R5 = 0242h
If R5=0240h, then after execution of  R6 = 00CD, R5 = 0241h

72. [0308]=ABCD, R7=0308h, R6=4321h
 R6= EEEEh, R7=0308h
 R6=EEEEh R7=030Ah
 R6=00EEh, R7=0308h
 R6 = 00EEh, R7=0309h

73. Memory related addressing modes (3): Indexed ( register relative; or base indexed)
Address is given as the addition of a number X and contents of a CPU
Notación RTN: (Reg +X)
If R6=2340h, (R6+4)  # 654Ah means “store the word number 654Ah in memory at address given by R6+4, that is, 2344h
Msp430 notation: X(Rn)
If R6=2340h, mov #654Ah, 4(R6) yields [2344h] = 654A
If R6=2340h, mov #654Ah, 0(R6) yields [2340h] = 654A
0(R6) is equivalent and is valid for destination!
Indexed mode is very useful for array type data

74. EXAMPLE for use of indexed mode: lookup table.1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
x^2 16 25 36 49 64 81
100
121
144
169
196
225 9 81 8 64 7 49 6 36 5 25 4 16 3
0304h+2
0304h+1 1
0304h+0
ORG 0x0304
Squares DB 0,1,4,9,16.25,36,49,64,81
------
mov # 7,R5
add.b Squares(R5), R8

75. Examples (1/2) Direct mode: Register indirect:
Word size data address and content before each example (all hex notation): [0308]= 23FE, [030A]=012D
Direct mode:
mov 0308h, R6  R6 = 23FE
If R6 = 9ABC , then mov R6, 0308h  [0308] = 9ABC
Register indirect:
If R5 = 0308, then
R6  R6=23FE, R5=0308
0x030A  [030A]= 23FE

76. Examples (2/2) Indexed Mode:
Word size data address and content before each example (all hex notation): [0308]= 23FE, [030A]=012D
Indexed Mode:
If R5 = 0308, and R6= 3FEC before each instruction then
mov 2(R5), R6  R6=012D, R5=0308
mov 0(R5), 0x030A  [030A]= 23FE
mov R6, 2(R5)  [030A] = 3FEC, R5= 0308, R6 = 3FEC
mov # 128, 0(R5)  [0308] = 0080
Comments: Indexed mode is very handy for arrays.