1. Multiprocessor & Multicomputer

2. Motherboard

3. CPU

4. Multi-core

5. multiprocessor

6. multicomputer

7. Computer Arithmetic

8. Addition & Subtraction Signed - Magnitude

9. Hardware Architecture
Cont.…
Hardware Architecture

10. Cont.…
Flowchart

11. Addition & Subtraction Signed – 2’s Complement

12. Multiplication Signed - Magnitude

13. Cont.…

14. Cont.… Example Number1 X Number 2 Multiplicand in B
Multiplier in Q E A Q SC
shr(EAQ)
Final Product in AQ

15. Multiplication Signed – 2’s Complement (Booth’s)

16. Cont.…
Flowchart

17. Cont.… Example Number1 X Number 2 Multiplicand in BR
Multiplier in QR Qn Qn+1 AC QR SC
Ashr(AC & QR)
Final Product in AC QR

18. Division Signed – 2’s Complement

19. Cont.… Example

20. Cont.… Example

21. Cont.… Example

22. Array Multiplier ‘J’ is Multiplier ‘k’ is Multiplicand J*k  AND gates
(J-1)*k  HA
Here, a is Multiplier
And b is Multiplicand

23. Addition & Subtraction Floating Point Numbers
Hardware Architecture
The algorithm can be divided into four consecutive parts:
 1. Check for zeros.
 2. Align the mantissas.
 3. Add or subtract the mantissas
 4. Normalize the result

24. Flowchart

25. Multiplication Floating Point Numbers
The algorithm can be divided into four consecutive parts:
 1. Check for zeros.
 2. Add the Exponents.
 3. Multiply the mantissas.
 4. Normalize the Product.

26. Flowchart

27. Division Floating Point Numbers
The algorithm can be divided into four consecutive parts:
 1. Check for zeros.
 2. Subtract the Exponents.
 3. Divide the mantissas.

28. Flowchart

29. Derivation of BCD Adder

30. Block Diagram of BCD Adder
Cont.…
Block Diagram of BCD Adder

31. Decimal Addition & Subtraction
One stage of Decimal Arithmetic Unit

32. Parallel Decimal Addition
All Serial Addition

33. Digit Serial and Bit Parallel Addition

34. Decimal Multiplication & Division
Registers for Decimal Arithmetic Multiplication and Division

35. Flowchart for Multiplication

36. Flowchart for Division