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Choix d’une architecture de CAN adaptée au MAPS

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Presentation on theme: "Choix d’une architecture de CAN adaptée au MAPS"— Presentation transcript:

1 Choix d’une architecture de CAN adaptée au MAPS
Journées VLSI/PCB/FPGA/outils 2010

2 Outline Context (collaboration IN2P3&IRFU)
Presentation of both architectures Study of references for several parallel ADCs Comparison of performances Proposition of a new architecture Conclusion 22/06/2010

3 Context MAPS with discriminator for the innermost layer of vertex detector MAPS with ADC for the outer layers of vertex detector Pitch : ~35 µm Resolution of ADC : 4 bits   < 3 µm LSB : 4 mV Number of columns : 512 Readout time for 1 line : 100 ns i.e. 10 MSamples/s 22/06/2010

4 CDS and amplification stage
Architecture of PAD Collaboration between LPSC Grenoble and IPHC Strasbourg Pipeline ADC 2 x 1.5 bits pipeline stage 1 x 2 bits flash stage CDS and amplification stage 22/06/2010

5 Architecture of MAD Developed at IPHC Strasbourg Multibits ADC ADC
SAR like 2,3 or 4 bits CDSA CLK Vin Vmc ADC Vrefp C 2C 4C 8C 4 bits DAC: 16 capacitances ( total of 3.2 pF) Vrefn Out DAC 22/06/2010

6 Issue of Multi-channel ADCs
One ADC per column Unique references for all ADCs Due to RC line, references take time to be stabilized during switch activation This issue has been seen in Phase 1 and corrected in Mimosa 26 by splitting the references in 4 parts R C 2 cm 22/06/2010

7 Multi-channel ADCs for PAD
There are 3 references in the amplification stage which are sensitive to RC line (2 cm) The references are switched on/off every 50 ns (100 ns/2) to give a frequency of 10 MSamples/s The references split into two parts (256 ADCs)  Sufficiently stable with LSB of 4 mV. Maximum of dispersion between channel 1 and channel 256 is MSamples/s 6 buffers (2 parts x 3 references) are necessary 22/06/2010

8 Multi-channel ADCs for PAD
22/06/2010

9 Multi-channel ADCs for MAD
There are 2 references in the DAC which are sensitive to RC line (2 cm) The references are switched on/off every 20 ns (100 ns/5) to give a frequency of 10 MSamples/s The references split into four parts (128 ADCs)  Sufficiently stable with LSB of 16 mV. Maximum of dispersion between channel 1 and channel 128 is MSamples/s during comparison Maximum of dispersion between channel 1 and channel 128 is MSamples/s during reset of DAC 8 buffers (4 parts x 2 references) are necessary The CDS and amplification stage must have a gain multiplied by 2 22/06/2010

10 Multi-channel ADCs for MAD
22/06/2010

11 Comparison of performances
PAD MAD Voltage supply 3 V Technology AMS CMOS 0,35 µm Resolution 4 bits 4,3,2 bits Sampling Rate 10 MSample/s Static Power 395 µW / columns 300 µW / columns Dynamic Power 118 µW / columns 687 µW / columns (pixel hit) 159 µW / columns (no hit) Dimensions (estimation) 1050 µm × 35 µm2 (30% digital part) 950 µm × 35µm2 (40% digital part) LSB 4 mV 16 mV Gain CDSA 4 16 Number of Analogue Buffers 6 8 Power of Analogue Buffers 36 mW 48 mW Total Power (576 columns) 300 mW 570 mW all pixels hit 280 mW 30 pixels hit 265 mW no pixel hit 22/06/2010

12 Proposition of a new architecture
8 references for all ADCs There is the same number of references The DAC which is the largest part in MAD is replaced by an AMUX The estimated size is 550 µm by 35 µm (66 % digital part) The precision is good enough for a LSB of 4 mV All the references are the same for all ADCs CDSA CLK Vin Vmc ADC AMUX Vref1 Vref2 Vref8 FSM Results on 4,3 or 2 bits 22/06/2010

13 Conclusion The choice between a single PAD and a single MAD is difficult because the performances are closed The new architecture (modified MAD) is adapted to a large number of multi-channel ADCs (same conclusion as IRFU) The references are generated in the chip with JTAG DACs The precision and noise performances are adequate with the discriminator that does not use an amplifier after the pixel The simulation was performed with APS Available with MMSIM 7.1 Multiprocessor simulator for large circuit Spectre compatible The same precision than spectre Less than 1 minute of simulation for 512 ADCs (with a 8 cores CPU) 10 minutes with spectre 22/06/2010


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