1. OMEGAPIX 3D IC prototype for the ATLAS upgrade SLHC pixel project Journées VLSI 22th June, A. Lounis, C. de La Taille, N. Seguin-Moreau, G. Martin-Chassard, D. Thienpont (LAL Orsay)

2. Planar Pixel Project for Super ATLAS
Smaller b-layer radius & potential increased
luminosity (x10) → need a re-design
Smaller pixel size 50x400μm → 50x50μm
(reduce pixel cross section)
Material reduction & improve of active area
thin sensor : < 75 μm
reduce size of peripheral area of sensor & chip
low threshold (1000 e-), low noise (100 e-),
low power (3μW/pixel)
New technology
Chartered 130nm, Low Vt, better radiation tolerance
Tezzaron: 3D technology, wafer to wafer (alignment <1μm), face to face (via first), reduction of non active area, analog & digital substrate isolation
Why a
new chip ?
MPI Munich sensor
n+ on p-type substrate
Thikness ~100μm but <75 at term
OMEGAPIX chip
3D Tezzaron techno + 130nm Chartered techno
December 3, 2018
D. Thienpont ATLAS LAL

3. Subreticule D: LAL-Orsay contribution
OmegaPix is a prototype dedicated to two main goals:
Firstly: study and validate the new Chartered techno and the 3D process
Tiers isolation, Chartered techno characterization (T typical, low Vt), yield, electrical and mechanical connections
Secondly: explore new solutions for the pixel chip for the ATLAS upgrade
low power, small pitch, low signal
→ It has been submitted in April 2009
FE-TC4
Analog
(Marseille)
OmegaPix
Analog
(Orsay)
OmegaPix
Digital
(Orsay)
FE-TC4
Digital
(Marseille)
Chip size
Height= 4.08 mm, Width =1.74 mm, Area = 7.1 mm²
Technology: 0.13 um Chartered
Power Supply: 1V / 1.2 V
December 3, 2018
D. Thienpont ATLAS LAL

4. OmegaPix: analog tier
To minimize power dissipation, power voltage has been reduced to 1.2 V for the analog part and 1 V for the digital (with the discri)
Discri is performed by three inverters, and to fix the threshold we use a DAC 5bits which tune the DC level at the output of the shaper
2nd gain
December 3, 2018
D. Thienpont ATLAS LAL

5. OmegaPix: Analog tier – Charge preamplifier
Cgd not precise: need of gain adjustment
VDD = 1,2 V
Parasitic capacitance Cgd performs the feedback capacitance: Cf = Cgd ≈ 1,6 fF. Ideal gain is 1/Cf -> 625 mV/fC
A paraphase structure has been used to fix the DC points and absorb the leakage current coming from the detector
Paraphase structure
Ib1 = 1 nA, Ib2 = 2 nA, Ib3 = 1 µA
December 3, 2018
D. Thienpont ATLAS LAL

6. OmegaPix: typical simulation
Simulation conditions: Qinj = 1000 e-
DAC: 1000 (only 2.5/0.5 nmos_1p5_lvt as 2nd stage), Vth = 800 mV
Transient response
Noise at the output of the shaper
2nd stage
DAC fixes the DC output voltage and so the threshold
DAC: 1000
Vth = 800 mV
282 mV
S/N =
Noise threshold = 50 e- to 130 e-
Preamplifier
Vmax = Q/C => 60 mV
59.6 mV
2 MHz
December 3, 2018
D. Thienpont ATLAS LAL

7. Preamplifier & 2nd stage: gain = f(Qinj)
Shaper gain = 0011, Vdac = 710 mV, Ileak = 1 nA
(mV)
Preamplifier output
DC level = 535 mV
leakage current : ~1 nA → DC level < Vref
rms Noise = 5.4 mV (65 e-)
S/N = 9 – 10
Qinj (N)
(mV)
280 mV
Vref = 600 mV
DC level = 613 mV
rms Noise = 20 mV (100 e-)
S/N = 6.5
2nd stage output
2Ke- in this config
Qinj (N)
December 3, 2018
D. Thienpont ATLAS LAL

8. Time over Threshold (ToT) & Latency
With ToT coded on 4 bits, we have:
ToT(1000 e-) = 8
ToT(2000 e-) = 15
ToT(3000 e-) = 15
ToT(4000 e-) = 15
ToT(5000 e-) = 15
ToT(6000 e-) = 15 …
(ns)
ToT
Qinj (N)
(ns)
Latency
4 Bunch Crossing
Time Walk = ~ 75 ns !
A good value of Latency and Time Walk would be < 25ns ! ! !
25 ns
25 ns
Qinj (N)
December 3, 2018
D. Thienpont ATLAS LAL

9. OMEGAPIX: different columns
Several column types have been designed allowing us to study various flavours of transistor types (normal, low VT, 3p3), noise, oscillations…
Columns 1 to 10: reference channels
Columns 11 to 18: various preamplifier transistor types have been integrated
Column 19 to 22: without variable gain
Column 23: discriminator has been removed
Column 24: shaper has been removed
At the first time, the sensor will not be bonded, nevertheless there is the possibility to inject charge via a pad
Some others possibilities are available…
December 3, 2018
D. Thienpont ATLAS LAL

10. Preamp: nominal – double - half
Preamplifier output
Latency
nom = nmos_3p3 5/1
double = nmos_3p3 10/1
half = nmos_3p3 5/0.5
ToT
December 3, 2018
D. Thienpont ATLAS LAL

11. Preamp: nominal – 1P5 – 1P5LVT
Preamplifier output
Latency
nom = nmos_3p3
nom1P5 = nmos_1p5
nom1P5LVT = nmos_1p5_lvt
ToT
December 3, 2018
D. Thienpont ATLAS LAL

12. OmegaPix: « Digital » tier
Digital tier has been designed by Yixian Guo from LPNHE (Paris). Each channel includes a 24 DFlipflop register: main tests will focus about the noise study
Read bus on out pad
Go to the next channel D_r pin
Q_r
D_r
1536 channels, 24 columns, 64 ch/col
64 channels
Q_r
D_r
Only one channel output can be viewed on the same time
Q_r
D_r
out
24 columns
December 3, 2018
D. Thienpont ATLAS LAL

13. While waiting for the chip
December 3, 2018
D. Thienpont ATLAS LAL

14. Analog memory
The analog memory stores all events even if no hit appears. When we write into a cell, the next is read. If there is a hit and if there is L1 trigger, then we keep this hit into a RS FlipFlop. Two fast OR are sent across the column and across the row.
Bus_write
BC0
BC1
BC2
BC3
BC(n-1)
BCn
or_column
vdd
Switches commands are common for all the matrix
or_row
L1 trigger
Select_row
120 memory cells for each channel
120 x 25 ns = 3 us
Select_col
Raz_sm
December 3, 2018
D. Thienpont ATLAS LAL

15. Readout scheme
clock
All triggered pixels have to be readout in less than 125 ns with this configuration ! L1
(1) Logic finds the rightmost column with hit and stores Then it select this column.
(2) Logic finds the rightmost pixel with hit and stores Then RSFF is erased.
7 clocks to readout a triggered hit.
Logic readout all the matrix or a sub-matrix.
December 3, 2018
D. Thienpont ATLAS LAL

16. Measurements and ongoing work
Firmware and LabView software are OK
Four test boards are wired
Measurements
Analog tier: preamp, shaper, discri + noise
threshold dispersion
Layers coupling
Chartered/Tezzaron techno characterization: transistor (LowVt, 3p3, 1p5, size), DAC linearity…
Ongoing work
Digital readout study and design
circular memory to store data up to L1
(submission for July in 2D)
only triggered hits readout
Test board with sensor from Munich
2D run possibility
1.7 mm
2.5 mm
Proto circular memory
December 3, 2018
D. Thienpont ATLAS LAL

17. BACKUP SLIDES
December 3, 2018
D. Thienpont ATLAS LAL

18. OmegaPix: dedicated test chip – Slow Control
24 columns, 64 channels/columns -> 1536 channels
14 SC bits/channel -> SC bits
2 SC bits/selectColumn -> 48 bits
SC in the entire analog matrix
In_test -> 1 bit
3 probes: preamplifier, shaper, discriminator -> 3 bits
DAC -> 5 bits
Shaper: variable gain -> 4 bits
Discriminator: mask -> 1 bit
-> 14 SC bits / channel
Slow control bits for one analog channel
December 3, 2018
D. Thienpont ATLAS LAL

19. Semi-analog memory: analog instance + digital data
Memory cell
Semi-analog memory: analog instance + digital data
10uA
December 3, 2018
D. Thienpont ATLAS LAL

20. Q leakage in memory cell
December 3, 2018
D. Thienpont ATLAS LAL

21. A « shaperless » analog front-end
Only simulation
No layout !
December 3, 2018
D. Thienpont ATLAS LAL

22. A « shaperless » analog front-end
(mV)
(ns)
Time Walk = 30 ns
Preamplifier output
Latency
25 ns
Qinj (N)
(ns)
ToT
Qinj (N)
rms Noise = 10 mV (120 e-)
V threshold = 80 mV
Consumption :
preamp = 2.4 uW
discri = 430 nW
total = 2.83 uW
Qinj (N)
December 3, 2018
D. Thienpont ATLAS LAL