1. FPGA Tools Course Basic Constraints

2. Objectives
Learn how to define basic timing constraints and pin assignments with the Timing Constraints GUI

3. Outline Introduction Pin Assignments The Period Constraint
The Offset Constraint
Summary

4. The Constraints Editor
Timing and Physical constraints are entered with the Constraints Editor
Alliance users: Select Utilities -> Constraints Editor in the Design Manager window
Usage:
Alliance - Select Design Manager -> Utilities -> Constraints Editor from the Design Manager
Foundation users: Select Start -> Products -> Xilinx Foundation Series -> Accessories -> Design Manager ->Utilities -> Constraints Editor

5. Types of Constraints Constraint commands can define:
Performance expectations
Pin assignments
Constraints control implementation, including place and route
Constraints can be entered by the Constraints Editor

6. Outline Pin Assignments Introduction The Period Constraint
The Offset Constraint
Summary

7. Pin Assignments in the Constraints Editor
Pads and Slew Rate can be assigned on a pin by pin basis
Place pin assignments late in the design cycle
Early pin locking can make obtaining performance objectives more difficult

8. Outline The Period Constraint Introduction Pin Assignments
The Offset Constraint
Summary

9. Period Constraints in the Constraints Editor
Clock Periods can be made by clicking on the Global tab and specifying a period length.
The Xilinx M1 software determines internal FPGA delays necessary to meet the timing constraints.

10. The PERIOD Constraint
This constraint covers all paths from a pad to a synchronous element (FF, Latch, or synchronous RAM), and paths between synchronous elements which are clocked by the referenced net.
Every synchronous element is effectively identified by forward propagation.
This constraint does not cover paths to output pads, but does cover paths from input pads to the synchronous elements.
Which paths are constrained by a PERIOD constraint in this circuit?
Forward propagation path
Paths controlled by PERIOD
RAM
OUT2
OUT1
CLK
CLK_IN Q D G
LATCH
FLOP
BUFG

11. Period Path Tracing PERIOD analyzes the following:
Synchronous element to synchronous element data path
PAD to synchronous element data path
Automatically accounts for inverters on clocks
Deals with unequal clock duty cycles
Synchronous element to PAD and PAD to PAD paths are not constrained by a PERIOD constraint
Clock Network to Clock Network uses Target Clock as Time Constraint
Question: Which constraint will control this path?
Answer: B_CLK
NET A_CLK PERIOD=20;
NET B_CLK PERIOD=40;

12. Outline The Offset Constraint Introduction Pin Assignments
The Period Constraint
The Offset Constraint
Summary

13. The OFFSET IN - BEFORE FPGA NET Din OFFSET = IN 20nS BEFORE CLK
This says that the Data to be registered in the FPGA will be available on the FPGA’s input Pad 20ns BEFORE the clock pulse is seen by the FPGA’s clock pad.
Therefore, the M1 tools will calculate the Maximum Allowable Din.
Din = OFFSET + internal CLK delay.
This constraint is best used when you know the maximum delay of Din that can be tolerated.
Note, that the Constraints Editor only writes an Offset In Before constraint.
CLK
UPSTREAM DEVICE
FPGA
Din
Data registered
in FPGA on
this edge.
Valid
20ns
Data Out
of DEV1 on

14. The OFFSET IN - AFTER FPGA NET Din OFFSET = IN 16nS AFTER CLK;
UPSTREAM DEVICE
FPGA
Din
This says that the Data to be registered in the FPGA will be available on the FPGA’s input Pad 16ns AFTER the clock pulse is seen by the Upstream Device.
Therefore, the M1 tools will calculate the Maximum Allowable Din.
Din = PERIOD - OFFSET + internal CLK delay.
This constraint is best used when you know the maximum external delay of the signal arriving at the FPGA’s input pin.
Convert this to an Offset In Before constraint by subtracting the external delay from the period.
16ns
Data registered
in FPGA on
this edge.
Data Out
of Upstream Device
on this edge.
Valid

15. The OFFSET OUT - AFTER FPGA NET Dout OFFSET = OUT 22nS AFTER CLK;
This constraint says that the Data to be registered in the Downstream Device will be available on the FPGA’s output Pad 22ns AFTER the clock pulse is seen by the FPGA.
Therefore, the M1 tools will calculate the Maximum Allowable Dout.
Dout = OFFSET - internal CLK delay.
This constraint is best used when you know the maximum delay on Dout that can be tolerated.
Note, that the Constraints Editor only writes an Offset Out After constraint.
DOWNSTREAM DEVICE
FPGA
Dout
CLK
Data clocked
into Downstream device on
this edge.
22ns
Data Out
of FPGA on
this edge.
Valid

16. The OFFSET OUT - BEFORE FPGA NET Dout OFFSET = OUT 25nS BEFORE CLK;
This says that the Data to be registered in the Downstream Device will be available on the FPGA’s output Pad 25ns BEFORE the clock pulse is seen by the Downstream Device.
Therefore, the M1 tools will calculate the Maximum Allowable Dout.
Dout = PERIOD - OFFSET - internal CLK delay.
This constraint works best when you know the maximum external delay of the data reaching the synchronous element of the Downstream Device.
Convert this to an Offset Out After constraint by subtracting the external delay from the period.
DOWNSTREAM DEVICE
FPGA
Dout
CLK
Data Into
Downstream device on
this edge.
25ns
Data Out
of FPGA on
this edge.
Valid

17. Offset Constraints in the Constraints Editor
Global Offset IN/OUT constraints can be made by clicking on the Global tab.
Remember that the Pad to Setup and Clock to Pad constraints minimize all input and output paths respectively.

18. Path Specific Offset Constraints
Path specific Offset IN/OUT constraints can be made by clicking on the Pads tab.
Path specific constraints can be used to optimize specific paths in the design without over constraining the design.

19. Synchronous Constraint Example
Question: If the external delay on an input signal is 14 ns, the external delay on output is 12 ns, and the design should perform with a period of 40 ns, what constraints should be placed on the design?
Determined by
Software
Determined by
Software
Tarrival 14ns
40ns
Tstable 12ns
ADD0_IN
FF1
FF2
ADD0_OUT
CLK 20 40 14
ADD0_IN
CLK 28
OUT1
Answer:
NET CLK PERIOD = 40;
NET ADD0_IN OFFSET = IN 14 AFTER CLK;
NET ADD0_OUT OFFSET = OUT 12 BEFORE CLK;

20. Constraint Recommendations
Avoid OVER-constraining the design
Design Performance suffers
Critical timing paths get the best placement and fastest routing options
As the number of critical paths increases, the ability to obtain the design performance objectives decreases
Run times increase

21. Outline Summary Introduction Pin Assignments The Period Constraint
The Offset Constraint
Summary

22. Summary
The Constraints Editor allows you to communicate design performance needs.
The PERIOD constraint limits the delay paths between input pins and synchronous elements, and paths between synchronous elements.
The OFFSET constraint limits the delay paths between input pins and synchronous elements, and paths between synchronous elements and output pins.

23. For More Information...
More information is also included in the AppLINX CD:
See AppLINX.pdf -> Development Systems Documentation -> M1 Documentation -> M1 Constraints Guide
Additional information is also in the Attributes, Constraints, and Carry Logic section of the Libraries Guide available from the DocuText Browser:
See Xilinx -> Online Books -> Libraries Guide
Refer to the Timing and Constraints Journal on the Xilinx website. Click on Customer Service and Support -> Expert Journals.
Advanced Timing Constraints will be covered tomorrow.

24. Questions Given the following: Fill in the constraints below: IC 1
Clock Frequency = 20 MHz
Tarrival = 31 ns = delay from CLK to Input pin D1 of IC2
Tstable = 27 ns = delay (including setup) from O1 to D pin of FF3 (IC3)
Fill in the constraints below:
NET_______PERIOD = ________NS
NET_______OFFSET = IN ________ AFTER CLK
NET_______OFFSET = OUT ________ BEFORE CLK
IC2: FPGA
IC 1
IC 3 Q C3 C1 C4 CK D1 O1
CLK D C2