Fundamentals of Computer Organisation and Architecture

Fundamentals of Computer Organisation and Architecture
The CPU

Internal Structure System Clock Control Circuits Instruction Decoder CIR SR Control Signals PC Internal Buses Internal Clock Program Control Unit Arithmetic & Logic Circuits Arithmetic-Logic Unit R0 R7 General Purpose Registers Data MBR MAR PROCESSOR Internal Buses Control Bus Address Bus Data Bus Fundamentals of Computer Organisation and Architecture: The CPU

Internal Structure Program Control Unit Arithmetic and Logic Unit
System Clock Control Circuits Instruction Decoder CIR SR Control Signals PC Internal Buses Internal Clock Program Control Unit Arithmetic & Logic Circuits Arithmetic-Logic Unit R0 R7 General Purpose Registers Data MBR MAR PROCESSOR Internal Buses Control Bus Address Bus Data Bus Program Control Unit Arithmetic and Logic Unit Registers Internal Clock Internal Buses Logic Gates Fundamentals of Computer Organisation and Architecture: The CPU

Internal Structure: Program Control Unit
This section of the processor fetches program instructions from main memory Decodes them, and then executes them One at a time System Clock Control Circuits Instruction Decoder CIR SR Control Signals PC Internal Clock Program Control Unit Fundamentals of Computer Organisation and Architecture: The CPU

Internal Structure: Arithmetic and Logic Unit
Performs arithmetic and logical operations on data Additions and subtractions Fixed/floating-point arithmetic Boolean Logic (AND, OR) Shift operations Arithmetic & Logic Circuits Arithmetic-Logic Unit Fundamentals of Computer Organisation and Architecture: The CPU

Internal Structure: Registers
Very fast memory locations Available within the CPU (and some input/output devices) Can store data, memory addresses, and more Address Bus Data Bus PROCESSOR MAR MBR Program Control Unit CIR SR R0 R7 General Purpose Registers Fundamentals of Computer Organisation and Architecture: The CPU

Internal Structure: Clock
Gets the ‘time’ from the system clock (Directly or indirectly) PROCESSOR Internal Clock Program Control Unit System Clock Fundamentals of Computer Organisation and Architecture: The CPU

Internal Structure: Internal Buses
Mediums of travel for data between components of the CPU Data has to move around the CPU using these ‘lanes’ PROCESSOR Program Control Unit Internal Buses Internal Buses Internal Buses Internal Buses Fundamentals of Computer Organisation and Architecture: The CPU

Internal Structure: Logic Gates
Control the flow of data PROCESSOR Program Control Unit Arithmetic-Logic Unit Logic Gates These control the flow of data Fundamentals of Computer Organisation and Architecture: The CPU

Internal Structure: Register Types
General-purpose Registers (R0, R1, etc.) Available to store temporary program data by programmers Not assigned a specific role by processor designer R1 is register store having address 1 Not to be confused with memory location having address 1 R0 R7 General Purpose Registers Accessed with Instructions LOAD STORE ADD There are two kinds of Registers present within the Processor. General-purpose registers (R0, R1, etc.) are available for the programmer to use in programs to store data temporarily. They have not been assigned a specific role by the processor designer. R1 is register store having address 1; do not confuse it with memory location having address 1. General-purpose registers are accessed with instructions such as LOAD, STORE and ADD. Fundamentals of Computer Organisation and Architecture: The CPU

Internal Structure: Register Types
Dedicated Registers Assigned specific roles by processor designer Assist in processor operations Some read / manipulated by programmers Assigned specific role by processor designer CIR SR Program Control Unit MBR MAR Address Bus Data Bus Dedicated Registers SP MAR PC MBR SR ACC CIR The other kind of registers are known as Dedicated Registers. Some of which may be read or manipulated by programmers. These registers have been assigned specific roles by the processor designer to assist the processor’s operations. Programmers may read or manipulate some but not all of these registers. Fundamentals of Computer Organisation and Architecture: The CPU

Internal Structure: Dedicated Registers
Stack Pointer (SP) Points to Stack holding: Return addresses Procedure or function parameters Local variables Accessed when a procedure/function is called, or an interrupt is serviced Program Counter (PC) Points to next instruction to be fetched and executed Stack Pointer (SP) The SP is accessed by a procedure or function call or a serviced interrupt. It points to a stack of return addresses, procedure or function parameters, and variables local to the processor Program Counter (PC) The PC points to the next instruction to be fetched and executed Fundamentals of Computer Organisation and Architecture: The CPU

Internal Structures: Dedicated Registers
Status register (SR) Holds condition codes Indicate outcome of operations with a Flag Holds status information Are interrupts enabled or disabled? Status Register (SR) The SR holds condition codes that indicate the outcome of operations or status information, such as the result of an arithmetic operation (positive, negative, zero, overflow result) or whether an interrupt is enabled or disabled. These are stored as flags accordingly. Also status information such as whether interrupts are enabled or disable, is indicated in the status register. Arithmetic Operation Flags: Positive Negative Zero Overflow Result Fundamentals of Computer Organisation and Architecture: The CPU

Accumulator (ACC) Holds result of current set of calculations Current Instruction Register (CIR) Holds current instruction to be executed while it is decoded & executed Accumulator (ACC) The ACC holds the results of the current calculations. Current instruction register (CIR) Holds the current instruction to be executed while it is decoded and executed ADD #36: Add number 36 to current contents of Accumulator register Store result in Accumulator Fundamentals of Computer Organisation and Architecture: The CPU

Memory address register (MAR) Holds address of memory location currently being accessed by processor Memory buffer register (MBR) Holds data item from memory location currently being accessed by processor Memory address register (MAR) Holds the address of the memory location currently being accessed by the processor Memory buffer register (MBR) Holds the data item being transferred to or from the memory location currently being accessed by the processor Fundamentals of Computer Organisation and Architecture: The CPU

Fundamentals of Computer Organisation and Architecture: The CPU
The System Clock Every computer has own system clock Quartz-controlled oscillator Pulse Supplies timing signals at a fixed rate Other timing signals derived from oscillator Regulate rate at which instructions are executed Synchronise operations of various computer components System clock Quartz are most abandoned minerals on the Earth containing silicon and oxygen. They are capable of converting any mechanical force into electric force and vice versa, which is knows and Piezo-Electric property. Also used to convert electric force into sound waves and vice versa. A slice, or wafer, of quartz crystal will generate an electric current when it is subjected to pressure. Conversely, a wafer connected in an alternating electric circuit will expand and contract, or oscillate, at a fixed frequency. This frequency depends on the thickness of the wafer. Thin wafers oscillate at higher frequencies than thick ones. Every computer has its own system clock, a quartz-controlled oscillator that supplies timing signals at a fixed rate. Other timing signals are derived from this oscillator. These timing signals are used to regulate the rate at which instructions are executed to synchronise the operations of various computer components. Clock rates, frequencies, or speed are expressed in megahertz (MHz) or gigahertz (GHz). Generates regular pulses to synchronise all the system events and determine the speed at which processing can occur. Basic measure of perfomrance is MHz, million of cycles per second. Clock Rate Expressed in: Frequency Megahertz (MHz) Speed Gigahertz (GHz) Fundamentals of Computer Organisation and Architecture: The CPU

The System Clock Processors execute instructions at a given frequency 1GHz, 2GHz, 3GHz, 3.6GHz Known as Click Speed / Click Frequency Instructions executed In fixed number of Clock Ticks / Click Cycles Some instructions require more clock ticks than others Clock Ticks Supplied by System Clock Internal Clock Inside Processor Uses Frequency-multiplying Circuits Raises frequency of System Clock Ticks System clock and clock speed Processors are designed to execute instructions at a given frequency, e.g. 1GHz.This is known as the click speed or click frequency of the processor. A processor executes a particular instruction in a fixed number of clock ticks, or click cycles. Some instructions require more clock ticks than others. The system clock supplies the clock ticks that a processor requires to execute instructions. The system clock’s frequency is raised to the rate that the processor requires by frequency-multiplying circuits. This is done inside the processor, so this clock is called an internal clock. Fundamentals of Computer Organisation and Architecture: The CPU

The System Clock System Bus Requires Clock Ticks Transfer binary words between processor and main memory or an I/O controller Bus tick rate should match processor tick rate Bus is often slower Clock ticks derived from system clock Supplied to electronics of System Bus Distributed to main memory to support operations Clock speed doubles roughly every year 1990 Intel MHz 2000 Intel Pentium III 1GHz System clock and clock speed The operation of the system bus also requires clock ticks when a binary word is transferred between the processor and main memory or an I/O controller. Ideally, the tick rate of the bus should match the tick rate of the processor but often it is lower. Clock ticks derived from the system clock are supplied to the electronics of the system bus. Similarly, clock ticks are distributed to main memory to support its operations. Computer click speed has been doubling roughly every year. The Intel 8088 found in many computers around 1990 ran at 4.77 MHz. The 1 GHZ mark was passed in 2000 with the Pentium 3. Fundamentals of Computer Organisation and Architecture: The CPU

Effecting Process Speed
Binary Machine Code = language of computer Binary Word Consists of Binary Digits Word length = Number of digits in word Binary Words Instructions Memory Addresses Characters Integer Numbers Pixel Colours Digitised Sound Samples Word Length The language of the computer is binary. The computer works with binary words which are codes for instructions, memory addresses, characters, integer numbers, colours of pixel and digitised sound samples. Each binary word consists of binary digits. An example of a binary word is (base 2). The subscript 2 means that the pattern of 1s and 0s is a binary word. The word length is simply the number of digits in the word. Binary Word (base 2) Subscript 2 means pattern of 1s and 0s = Binary Word Fundamentals of Computer Organisation and Architecture: The CPU

Number of signal wires or lines allocated to a bus One signal wire represents one binary digit (1 or 0) More wires means more binary digits Increasing Bus Width Increases word size / length More Wire = Longer Words 6 wires (base 2) 8 wires (base 2) 32 wires (base 2) Bus width Bus width refers to the number of signal wires or lines allocated to a bus. The signal on an individual line represents one binary digit i.e. a 1 or a 0. Therefore, more wires means more binary digits, e.g. six wires means a word of six binary digits such as base 2. Thus the word size or word length that can be accommodated on a bus increased with increasing bus width (see table below). The number of binary digits in a word transferred over a bus is the same as the number of wires in the bus. Fundamentals of Computer Organisation and Architecture: The CPU

No. wires in bus, n No. bits in a word on the bus No. different binary words, 2n No. different binary words as a power of 2 Example binary word on bus Largest word counting in denary (2n – 1) 1 2 21 4 22 10 3 8 23 101 7 16 24 1100 15 256 28 255 65,536 216 65,535 20 1,048,576 220 …. 1,048,575 16,777,216 224 16,777,215 Bus width Bus width refers to the number of signal wires or lines allocated to a bus. The signal on an individual line represents one binary digit i.e. a 1 or a 0. Therefore, more wires means more binary digits, e.g. six wires means a word of six binary digits such as base 2. Thus the word size or word length that can be accommodated on a bus increased with increasing bus width (see table below). The number of binary digits in a word transferred over a bus is the same as the number of wires in the bus. Fundamentals of Computer Organisation and Architecture: The CPU

Processor / Microprocessor performance How quickly a task can be completed Speed of other components must equal processor Measured approximately Assess running of standard programs on processor How many machine operations completed per unit time Effects of click speed, word length and bus width on performance For a processor or microprocessor, performance means how quickly a task can be completed, all other things being equal. It can be measured approximately by running some standard programs on the processor and assessing how many machine operations are completed per unit time. The unit that is used is giga-ops per second (GOPS) or mega-ops per second (MOPS); here giga means 10 to the power 9 and mega means 10 to the power 6 Unit of Measure Giga-ops (GOPS) Mega-ops (MOPS) Fundamentals of Computer Organisation and Architecture: The CPU

Execution of machine code Twice as fast on 2GHz Processor than 1GHz (When all components are of equal speed) Assuming One instruction executes in one Clock Cycle / Tick Clock Cycle 2 GHz Processor = Half-duration of 1 GHz Processor Half time to execute an instruction Increasing clock speed All other things being equal, a processor with clock speed or frequency of 2 GHz should execute the same machine code program twice as fast as a processor from the same family with clock speed 1 GHz. This makes sense if we assume that each machine code instruction is executed in one clock cycle, or tick, in both processors. As the 2 GHz processor’s clock cycle is half the duration of the 1 GHz processor’s clock cycle, it will take half the time to execute an instruction. Fundamentals of Computer Organisation and Architecture: The CPU

A limit set on clock frequency Heat generated in chip by electric pulse Higher click frequencies fail to dissipate heat quick enough Problem worsens when More transistors are packed into the same space Increased power consumption Increased heat Heat affects Moore’s law on single processor performance Limits on clock speed A limit has to be set on clock frequency, because the heat generated in the chip by higher click frequencies cannot be removed quickly enough. The problem is made worse when more transistors are packed into the same space. This has caused a deviation from Moore’s Law. The reason for this is that packing more transistors into the same area increases the power consumption, which results in more heat. A similar consequence occurs when the clock frequency is increased. Fundamentals of Computer Organisation and Architecture: The CPU

If Transistor Density and Clock Frequency continued to increase Heat generated per square centimetre eventually surpass sun’s surface Limits on clock speed If transistor density and clock frequency continued to increase, it would eventually generate more heat per square centimetre than is generated on the surface of the sun. Fundamentals of Computer Organisation and Architecture: The CPU

Current strategy Increase in transistor density Allows more than one processor on microprocessor chip These processors called cores Operate at lower frequencies than single-core processors Overcome clock frequency heating problem More than one processor per chip Multiple tasks can be run in parallel Single task split across several processors Ideal for Multimedia Work Microsoft Windows Movie Maker 2.0 Adobe Photoshop CS Significant performance improvement on multicore systems Multicore microprocessors The strategy now is to use the increase in transistor density to put more than one processor onto the microprocessor chip. These processors are called cores and operate at lower frequencies than single-core processors to overcome the heating problem caused by clock frequency. With more than one processor per chip, multiple tasks can be run at the same time or a single task can be split across several processors. Multicore processors are ideal for multimedia work. Microsoft Windows Movie Maker 2.0 and Adobe Photoshop CS are example of widely used applications that show significant performance improvement on multicore systems. Fundamentals of Computer Organisation and Architecture: The CPU

Size of Processor Registers Bigger word length Measured in Word Length Bigger operands Affect processor’s speed performance Bigger results General-purpose and Accumulator When operands and results exceed register word length Can perform Arithmetic Operations Usually have similar word length Extra processing required Split operands and results across several registers Typical modern processor word lengths Reduces speed performance 32 bits 64 bits Increasing word length The word length of its registers affects the processor’s speed performance. The registers that can do arithmetic operations – the general-purpose registers and the accumulator – usually have a similar word length. Typical word lengths are 32 bits and 64 bits in modern processors. The bigger the word length, the bigger the operands and results they can accommodate. When operands and results exceed the word length of the registers, extra processing must be done to split operands and results across several registers. This reduces speed performance. Fundamentals of Computer Organisation and Architecture: The CPU

Registers Store binary codes for main memory addresses Number of registers affect number of bytes or locations of main memory that can be used Longer word More binary codes More memory bytes can be used / addressed PC and MAR Main registers Address main memory Increasing word length Registers used to store the binary codes for main memory addresses affect the number of bytes or locations of main memory that can be used. A longer word means more binary codes and therefore more memory bytes that can be used, i.e. addressed. The main registers used for addressing main memory are the program counter and the main address register. Fundamentals of Computer Organisation and Architecture: The CPU

Worst time penalty In System Bus Between processor and main memory If complete instruction exceeds current instruction register’s word length System Bus must be used again To transfer one more operand words into other registers Slows down processor performance Increasing bus width The worst time penalty occurs in the system bus between the processor and main memory. If the current instruction register’s word length is not high enough o hold a complete instruction, the system bus must be used again to transfer one more operand words into other registers, which slows down the performance of the processor. Fundamentals of Computer Organisation and Architecture: The CPU

System Bus Bottleneck More wires Larger the data word or instruction word transmitted in one go Fewer transmissions required Von Neumann computer A data or instruction word passes along data bus Wider data bus improves speed performance Address words pass along Address bus Wider address bus allows longer address words More memory can be addressed Increasing bus width The system bus is the bottleneck. The larger the data word or instruction word that can pass along its length in one go, the fewer the number of times it needs to be used. In a von Newmann computer, a data or instruction word passes over the data buys. A wider data bus should improve a computer’s peed performance. Address words pass along the address bus. A wider address bus allows longer address words, so more memory can be addressed. Fundamentals of Computer Organisation and Architecture: The CPU

Processor Transistors Number of wires restricts Binary Word size Number available to compute in every pulse Only one signal may travel Bus at any one time Increased number, increases heat Clock Pulse Register Size Greater frequency of clock ticks increases heat Availability of Registers within CPU Overflow transferred to Main Memory Only as fast the slowest component Bus Width Due to the nature of the Architecture in the CPU there are four points of constraint, otherwise known as bottlenecks: Processor transistors The number of transistors built into a Processor restrict the speed of computation Increased number, increases heat Register size The number of available memory registers within the Processor restrict the amount of data that can be stored inside the Processor during computation. When more data needs to be stored, it has to be transmitted along the Data Bus to Main Memory. That transmission slows processing Bus width Two things restrict data flow in the Bus. Firstly, the number of wires available to each Bus restricts the size of the word in the signal, and secondly, only one signal may use the Bus at any one time Clock Pulse The internal speed of the CPU is controlled by the Internal Clock, which controls signal flow with its ticks, which send the electrical pulse. The faster the pulse, the more electricity is passed and the hotter the CPU becomes Only as fast as the slowest component A computer is only as fast as its slowest component, so regardless of processor speed, if another component or a particular Bus has its own speed restrictions, this can hamper overall System speed Fundamentals of Computer Organisation and Architecture: The CPU

von Neumann Stored Program Concept
Proposed in 1945 by John von Neumann & Alan Turing Program must be resident in main memory to be executed Machine code instructions : Are fetched one after another From main memory in sequence Are executed one at a time in the processor First Stored Program 1948 – SSEM (Baby) CRT Output Stored program concept Both von Neumann and Alan Turing proposed the stored program concept in They detailed that in order for a program to be used, or executed, by a processor it must be resident within main memory. Therefore, machine code instructions that can be understood by the processor must be fetched, one by one in the correct sequence, from main memory. In sequence each line is then executed by the processor. The machine code fetched from a single memory location can be interpreted by the processor as either data or instructions. Therefore, the processor is instructed in the use of arithmetic or logic functions (telling the processor what to do), and it is issued with data, such as numbers or letters. This was put into practice in 1948 after two years of development by Kilburn and Williams, who developed the use of a CRT (Cathode Ray Tube) to act as memory. The world’s first stored program concept computer was the Manchester Small Scale Experimental Machine (SSEM), or “Baby”. Fundamentals of Computer Organisation and Architecture: The CPU

Processor instructed to perform arithmetic and logical operations Instructions represented by Binary / Machine Code Instructions and data stored in same way Bit pattern could be number 4616 letter F Instruct Processor to perform addition ADD, SUBTRACT, AND, OR Stored program concept The processor is instructed to perform arithmetic and logical operations such as ADD, SUBTRACT, AND and OR. These computer instructions are represented by numbers called machine code instructions and are stored in the same way as data. Thus a bit pattern such as might represent the number 46, or the letter F as data but it could also be used to tell a processor to perform an addition. Thus a single memory location hols values which can be interpreted as data or as instructions by the processor in von Neumann computer Hexadecimal: 46 Denary: 70 which is ASCII code for letter F Fundamentals of Computer Organisation and Architecture: The CPU

A serial machine Instructions and data fetched in sequence, one at a time Single shared memory Program instructions and Data Shared Data Bus Program Instructions and Data Processor Main Memory Addresses Data and Instructions In the first instance, the von Neumann Architecture came into play, with what is now known as the von Neumann stored program computer. It immediately hit upon what is known as the von Neumann Bottleneck. The von Newmann stored program computer is a serial machine. Serial means that instructions and data are fetched one after another, one at a time. The von Neumann computer has a single memory shared between program instructions and data. Data and instructions travel along a shared data bus as shown in the diagram below. Fundamentals of Computer Organisation and Architecture: The CPU

The Fetch-Execute Cycle
Programs Instructions executed in sequence Ensuring smooth execution Activities synchronised Internal Clock Instruction Execution Cycle Look at each instruction Decode instruction Act upon instruction Repeat process until program is complete We have covered the Processor now in great depth. As the CPU is the centre of everything and the Processor, its brain, the last thing we need to understand is how it does what it does. This process is known as the Fetch-execute Cycle. Each instruction is looked at in turn by the Processor Each instruction, in turn, is then decoded by the Processor The Processor acts upon the current instruction The process is then repeated, with the Program Counter incrementing and the next instruction being retrieved from memory Smooth execution is maintained within the Processor by the synchronisation of all the activities. This is down to the Internal Clock maintaing the electrical pulse every cycle. Fundamentals of Computer Organisation and Architecture: The CPU

Internal Clock (Control Unit) Regular pulse on System Bus Specific frequency Equidistant pulses gap Actions on pulse Memory Registers ALU CU Data Bus Address Bus Control Bus System Bus CPU Bus Clock pulse frequency Linked to Processor clock speed Higher clock speed = shorter pulse gap Commands kept in time across whole computer The Internal Clock is important because being connected directly into the Program Control Unit of the Processor it is necessary to produce a regular pulse inside the Processor and along the System Bus that keeps every component synchronised. The pulse is set at a specific frequency as required by the Processor, the gaps between the pulses are equidistant, which means that they are the same length of time. Actions of signal transmissions only occur on the pulse. Fundamentals of Computer Organisation and Architecture: The CPU

Programs Sequence of instructions Loaded into memory by user Executed by the CPU The brain Finite state machine CPU repeats three operations on each instruction Fetch Decode Execute Synchronises activities of processor FETCH DECODE EXECUTE The processor is a big Finite State Machine which ‘runs’ the programs placed in the memory by the user. The programs generate a sequence of instructions and these are executed one by one by the CPU. The CPU maintains the Fetch-execute cycle by repeatedly performing three operations in order to execute instructions in sequence: Fetch Decode Execute These activities are synchronised within the processor to maintain the work load, keep control of the instructions and ensure the sequence is followed. Fundamentals of Computer Organisation and Architecture: The CPU

Fetch  Decode  Execute Fetch Take required address from memory Store in CIR Increment PC - Point to next instruction - PC known as Pointer The CPU repeats the following three actions indefinitely: Fetch The processor maintains a pointer to the memory address location it has reached in the program. The pointer being the Program Counter. It fetches, or reads, a word from the memory address location which will be interpreted as an instruction. The instruction is stored in the Current Instruction Register. Normally, having read an instruction, the pointer, the Program Counter, is incremented and moves on to the next address. The CPU repeats the Fetch-execute Cycle indefinitely Fundamentals of Computer Organisation and Architecture: The CPU

Fetch  Decode  Execute Decode Control Unit - Checks instruction in CIR Determines - Op-code used - Addressing mode used - Actions required for execution Decode The instruction which has been read and stored in the Current Instruction Register is examined by the Instruction Decoder within the Control Unit, to see what it means. In practice the contents of the memory are just numbers, but remember that the processor can interpret a number as a coded way of specifying a certain action. Thus, for example, 0 could mean “add”, 1 could mean “subtract” etc. The decoding process takes the instruction or Op-code (operation code) and sets the appropriate control signals for the Finite State Machine. The FSM being all of those Transistors which will be used to determine the calculation or logic based upon the supplied data to follow. The CPU repeats the Fetch-execute Cycle indefinitely Fundamentals of Computer Organisation and Architecture: The CPU

Fetch  Decode  Execute Execute Actual actions depend on specified: - Instruction - Addressing mode Execute In the execution phase data is moved through the datapath into the Arithmetic Logic Unit and the requested calculation or logic decision is actually performed. This is based on the Instruction and Addressing Mode detailed in the Op-Code. After completing this sequence the processor goes back to fetch the next instruction and repeats the sequence. The CPU repeats the Fetch-execute Cycle indefinitely. The CPU repeats the Fetch-execute Cycle indefinitely Fundamentals of Computer Organisation and Architecture: The CPU

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