1. Short channel effects
Zewei Ding

2. Contents:
1、Abstract
2、Charge sharing models
3、Some harmful effects
4、Process to suppress the short channel effects

3. When short channel effect happens?
When L becomes noticeable comparable to Xsd and Xdd the source and drain depletion widths, respectively
What is short channel effect?
1、 Threshold voltage variation
2、 Carrier velocity saturation
3、 Deterioration of the subthreshold characteristics

4. Charge sharing models
Some assumptions:
1、the substrate is uniformly doped with concentration Nb
2、the source and drain are at zero potential, i.e, Vds=0
3、the source/drain junctions(depth Xj) are cylindrical in shape with radius Xj
4、the charges are shared equally between the gate and the source/drain junctions
5、the channel depletion width is equal to that of the source/drain depletion widths

5. Long-channel
Short-channel

6. Called the charge sharing factor
define so
We have
When the source and drain regions meet

7. For a given channel length ,
For a given channel length , depends upon the following device parameters:
The gate oxide thickness tox
The substrate doping concentration Nb
The junction depth Xj

9. Minor axis,
a is the side diffusion factor( )
Major axis,
Thus we can have another ,and more accurate

10. We take
fitting parameter
another fitting parameter K

11. Buried channel devices
Relatively small compared to the enhancement type devices

12. In terms of the expression for short channel voltage becomes
Anomalous threshold voltage characteristics
Qfso is the peak charge density
G0 is the characteristic length

13. Review:
1 charge sharing models and inprovment
2 factors that affect the Vth, tox,Nb and Xj

14. Some Harmful effects Impact ionization 1 High field-effect
Oxide charge
Substrate current
Subthreshold current
2 DIBL effect(Drain Induced Barrier Lowering)
Gate controled sensitivity
3 Punch-through
4 Parasitic transistor effect

15. Impact ionization
Oxide charge

16. Substrate current

17. DIBL effect

18. Punch through

20. Parasitic transistor effect

21. Conclusion:
1 Power limit
2 Size limit
3 Voltage limit

22. Process to suppress the short channel effects
Factors to be considered
Carrier mobility ,  gate oxide
Some process
LDD(lightly droped drain)
SOI( Silicon-On-Insulator)
Dual-gate

23. LDD

24. SOI
Single crystal of polycrystalline/ Amorphous
Single crystal substrate isolation
Silicon thin-film deposition

25. Dual-gate

26. Thank you