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Segment mezzanine I/O model

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Presentation on theme: "Segment mezzanine I/O model"— Presentation transcript:

1 Segment mezzanine I/O model
Cfg(1downto 0) Serial_Tx Data_A (15 downto 0) Serial_Rx Data_A_clk I2C_Sck Data_A _rdy I2C_Sda Data_A_ro Data_A_en-ack Jtag and config Data_B (15 downto 0) Data_B_clk Msg_data (7 downto 0) Data_B _rdy Msg_str0 Data_B_ro Msg_str1 SEGMENT MEZZANINE Data_B_en-ack B_cast_data (7 downto 0) Trig_req (1 downto 0) B_cast_str0 Trig_val (1 downto 0) B_cast_str1 Lt_data (7 downto 0) MII port Lt_Strobe LLP Status (7 downto 0) Tv_data (7 downto 0) Tv_Strobe GTS Status (7 downto 0) P3V3 P2V5 P1V5 GND

2 Core mezzanine I/O model
Cfg(1downto 0) Serial_Tx Data_A (15 downto 0) Serial_Rx Data_A_clk I2C_Sck Data_A _rdy I2C_Sda Data_A_ro Data_A_en-ack Jtag and config Data_B (15 downto 0) Data_B_clk Msg_data (7 downto 0) Data_B _rdy Msg_str0 Data_B_ro Msg_str1 CORE MEZZANINE Data_B_en-ack B_cast_data (7 downto 0) Trig_req (1 downto 0) B_cast_str0 Trig_val (1 downto 0) B_cast_str1 Lt_data (7 downto 0) MII port Lt_Strobe LLP Status (7 downto 0) Tv_data (7 downto 0) Tv_Strobe GTS Status (7 downto 0) P3V3 P2V5 P1V5 GND

3 GTS mezzanine I/O model
Cfg(1downto 0) Serial_Tx Serial_Rx I2C_Sck I2C_Sda Jtag and config Msg_data (7 downto 0) Msg_str0 Msg_str1 GTS MEZZANINE B_cast_data (7 downto 0) Trig_req (1 downto 0) B_cast_str0 Trig_val (1 downto 0) B_cast_str1 Lt_data (7 downto 0) MII port Lt_Strobe LLP Status (7 downto 0) Tv_data (7 downto 0) Tv_Strobe GTS Status (7 downto 0) P3V3 GND

4 Data readout engine Serializer To readout Engine 512x32 DPRAM
128 words/event 256 bytes/event 6 channels  1536bytes 16bit 100MHz Need 7.68µs (20µs 50KHz) Data readout engine 1536*4 = 6144 byte/Event 32bit 100MHz Need 15.36µs (20µs 50KHz) 4 pairs ; 8 I/O Data_A (15 downto 0) Serializer Deserializer Data_A_clk Data_A _rdy 32bit 32bit 512x32 DPRAM Data_A_ro Data_A_en-ack To readout Engine 9bit 9bit Data_A (15 downto 0) Serializer Data_A_clk Data_A _rdy Data_A_ro Data_A_en-ack Data_A (15 downto 0) Serializer From Trigger and readout engines Data_A_clk Data_A _rdy Data_A_ro Data_A_en-ack Data collector engine Data_A (15 downto 0) Serializer Data_A_clk Data_A _rdy Data_A_ro Data_A_en-ack

5 Trigger engine layout GTS CORE SEGMENT SEGMENT SEGMENT SEGMENT SEGMENT

6 ATCA carrier layout 10/100 GTS /SEGMENT Config µP CORE /SEGMENT
Ethernet Switch Data Mgm FPGA Zone 3 RTM GTS /SEGMENT TCLK PORT Config µP Dual FLASH Data Mgm FPGA To JTAGs CORE /SEGMENT ZONE 2 FAST ETHERNET MAIN FPGA SEGMENT Data Mgm FPGA ZONE 2 ETHERNET 1000 PCI Express Data Mgm FPGA SEGMENT 32x128M SDRAM 8x8M FLASH 32x512k Static DPRAM POWER & IPM IMP µP DC-DC +5  +3.3 DC-DC From -48v to +12/+5 4x DC-DC +5  +3.3 DC-DC +5  +2.5 DC-DC +5  +1.2

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