1. Dual Mode Logic An approach for high speed and energy efficient design
DML
Dual Mode Logic An approach for high speed and energy efficient design
Ramiro Taco
Bar – Ilan University Emerging Nanoscaled Integrated Circuits and Systems Labs
May 1, 2018

2. There is NO Free Lunch Performance Cost/Area Power Reliability
Security

3. Digital circuit level solutions – are they still relevant?
System
Most of today’s efficient solutions are proposed at the system and architecture levels.
New emerging technologies and devices are very promissing.
But what about circuit level solutions (logic families) in digital circuits?
CMOS logic haven’t been replaced since 80th
Attempts to replace CMOS with PTL, Dynamic and other logic styles did not succeed
Hardware security – alsmost all solutions are at the architecture level
Architecture
Gate
Circuit
Technology

4. Exploring the Energy-Delay Space
Is it possible to extend this pareto-optimal design curve by using an alternative logic family?

5. Dual Mode Logic for High Speed and Energy efficient Designs
CMOS and Dynamic Logic families
Characteristics
Dual Mode Logic
Principle of operation
Key aspects
Examples of DML use

6. A Few Words About Existing Logic Families
CMOS
Dynamic Logic
Rail to Rail, not ratioed, no voltage drops
Relatively small static currents
Very robust under Process Variations
2N transistors for N inputs  large capacitance
Low speed, high energy with standard sizing
Reduced transistor count and area
Reduced capacitance
Very fast
High Energy, Charge Sharing, glitches
Very high sensitivity to Process Variations

7. Dual Mode Logic (DML) Dynamic Logic CMOS Logic Dual Mode Logic
Speed
Robust & Low Energy
Dual Mode Logic
DML takes the best of both logics

8. DML – Principle of Operation
Static mode – like CMOS.
Dynamic mode – precharge and evaluation phases.

9. Classification of DML gate types
Type-A
Type-B
Type-A footed
‘1’
‘0’
Footers are used to link non DML domains (and reduce the precharge time)

10. DML – Topology and Sizing
Question:
If a DML gate is similar to a static gate (e.g. CMOS) and we add an additional transistor, so why is it:
Faster than CMOS in the dynamic mode?
Consumes less Energy in the static mode?
Answer:
The topologies are similar, but the sizing and logic optimization is different!
I.Levi, A. Belenky and A. Fish, “Logical Effort for CMOS based Dual Mode Logic (DML) gates”, vol. 22, issue 5, pp , IEEE Transactions on VLSI systems, 2013.

11. DML – Topology and Sizing
The evaluation is performed through parallel transistors – faster
The precharge transistor - in parallel to the stacked transistors
The stacked transistors (complementary network) will be sized to minimal widths to reduce intrinsic capacitances
NOR gates should be implemented as A-Type gates and NANDs as B-Type gates
A-Type
B-Type
complementary
NORs:
Better than
evaluation

12. Dual Mode Logic (DML) Two Modes of Operation
Dynamic
Static
Very Fast in the dynamic mode
Energy Efficient in the static mode
Can be switched between static and dynamic modes of operation according to system requirements and thus support applications in which a flexible workload is required OR
Save Power
Work Fast
Static
Dynamic
High Perform
High Power
Low Perform
Low Power
Static
Dynamic
High Perform
High Power
Low Perform
Low Power

13. DML – Evaluation (custom designs)
Failures
40nm, (20 FA Chain) Monte Carlo, VDD=300 mV. μCMOS=155n σCMOS = 84n. μDynamic=150n, σDynamic=141n. μDML_Static=190n σDML_Static = 80n. μDML_Dynamic=96n σDML_Static = 48n.
80nm NAND-NOR test chain energy consumption vs. VDD for CMOS, Domino & DML (Static & Dynamic)
Speed of FO-3 NAND-NOR Chains
I. Levi, A. Kaizerman and A. Fish, “Low Voltage Dual Mode Logic: Model Analysis and Parameter Extraction”, Microelectronics Journal, Elsevier, vol.44, issue 6, pp , June 2013.

14. Examples of DML use Applications where 2 operation modes are required
A phone processor example
mode 1 (low power, low frequencies) - speech processing or MP3 playback
Mode 2 (high speed) - HD video playback or gaming

15. Examples of use – one combined mode
128b Carry-Skip-Adder example
Operation of critical paths in the dynamic mode (leads to high speed)
Operation of non-critical paths in the static mode (leads to LP)
No Additional Circuitry for Control
I. Levi and A. Fish, “Dual Mode Logic Design for Energy Efficiency and High Performance”, IEEE Access, pp , vol1, 2013

16. Examples of use – one combined mode
Nominal voltage
Near Threshold Voltage
CMOS
CMOS
DML Stat
C.P DML Dyn
Ex1.5, Dx1.33
DML Stat
C.P DML Dyn
Ex2.5, Dx2

17. Examples of DML use Use # 2: Carry Look Ahead Adder example
The critical path of CLA is the longest carry route
The critical path is identified according to the inputs during operation and operated in dynamic mode (requires additional control circuitry)
I. Levi, O. Bass, A. Kaizerman, A. Belenky and A. Fish, “High Speed Dual Mode Logic Carry Look Ahead Adder”, Proc. IEEE International Symposium on Circuits and Systems,pp ,Seoul, Korea, 2012.

18. Examples of DML use
Use # 3 Combination of DML with Dual Mode Addition (DMADD) :
DMADD is probability based circuit architecture, comprising two addition modes [Wimer et all]
energy efficient, one-cycle mode
extended, occurs very infrequently and requires several clock cycles to properly add
DML avoids the extended, multi-cycle mode.
I. Levi et all, “A Low Energy and High Performance DM2 Adder”, IEEE Transactions on circuits and systems – I: Regular papers, July 2014

19. Examples of DML use Use # 4: Static and Dynamic operation combined
DML Multiplier Accumulator
Static and Dynamic operation are combined in different portions of the circuit
The MAC self adapts according to the critical path
1st stage: self adaptive mechanism embedded in the CB-PPRT
2nd stage: Prediction Circuit block controls the final adder

20. Questions ?