1. Day 27: November 6, 2013 Dynamic Logic
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 27: November 6, 2013
Dynamic Logic
Midterm 2
Avg: 53
Std Dev.: 17
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2. Today Clocking Dynamic (Clocked) Logic Strategy Form Compare CMOS
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3. Clocking
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4. Clocking Highlights Clock discipline simplifies logic composition
Abstracts many internal timing details
Just concerned with making clock period long enough
Breaking logic up with registers allows to run at high frequency – reuse logic
Discipline – keeping data stable around clock edge
Setup, hold time – determined by circuit
ClkQ delay for data come out of register
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5. Clocking Circuits typically operate in a clocked environment
Gives some additional structure we can exploit
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6. Dynamic Logic
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7. Motivation Like to avoid driving pullup/pulldown networks
reduce capacitive load
Power, delay
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8. Motivation Like to avoid driving pullup/pulldown networks
reduce capacitive load
Power, delay
Ratioed had problems with
Large device for ratioing
Slow pullup
Static power
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9. Idea Use clock to disable pullup during evaluation
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10. Discuss Use clock to disable pullup during evaluation
What happens when
/Pre=0, A=B=0
/pre=1, A=B=0?
/pre=1, A=1, B=0?
Sizing implication?
Concerns?
Requirements?
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11. Advantages Large device Single network Driven by clock not data/logic
Can pullup quickly w/out putting load on logic
Single network
Pulldown
Don’t have to size for ratio with pullup
Swings rail-to-rail
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12. Domino Logic
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13. Domino AND-OR
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14. Domino Everything charged high After inverter all inputs low
Why do we want this?
Disabled, waiting for an enabling transition
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15. Requirements Single transition All inputs at 0 during precharge
Once fires, it is done  like domino falling
All inputs at 0 during precharge
Precharge to 1 so inversion makes 0
Non-inverting gates
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16. Issues
Noise sensitive
Power?
Activity?
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17. Domino or4
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18. Domino Logic Performance Compare to CMOS cases? R0/2 input nor4 or4
nand4
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19. Dynamic OR4 Precharge time? Driving input
With R0/2
Driving inverter and self cap?
Output self delay?
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20. CMOS NOR4 Driving input Driving self cap? With R0/2
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21. CMOS NAND4 Driving input Driving self cap? w/ R0/2
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22. Discuss (time permit) Avoid inversion? Converting from CMOS?
Post-charge
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23. Observe Better (lower) ratio of input capacitance to drive strength
Particularly good for
Driving large loads
Large fanin gates
Harder to design with
Timing and polarity restrictions
Avoiding noise
Especially with today’s high variation tech.
Can consume more energy/op
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24. Admin Homework 7 out Withdraw date Friday …and due on Tuesday
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25. Idea Dynamic/clocked logic Only build/drive one network
Fast transition propagation
Spend delay (capacitance) on pullup off critical path of logic
More complicated, power
Reserve for when most needed
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