1. Byong Wu “Bernard” Chong Dec. 11, 2008
Power Efficient MIPS Processor Design Multiple Voltage MIPS Microprocessor
Jinpeng Lv
Xianzong Xie
Kyung Jin Park
Byong Wu “Bernard” Chong
Dec. 11, 2008

2. F08 ECE/CS 6710 Digital VLSI Design
Motivation (I)
There are wasted slack cycles on non-critical path
Critical path
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F08 ECE/CS 6710 Digital VLSI Design

3. F08 ECE/CS 6710 Digital VLSI Design
Motivation (II)
This is called multi voltage CMOS design. 39% to 57% reduction in power is reported (3.3V->1.9V)
Gates with low VDD
Now the non-critical path has less slack.
No performance loss
Multi-Voltage CMOS Circuit Design V. Kursun and E. Friedman
Volkan Kursun
University of Wisconsin-Madison, USA
Eby G. Friedman
University of Rochester, USA
# 2006 John Wiley & Sons, Ltd. ISBN:
Critical path 3
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F08 ECE/CS 6710 Digital VLSI Design

4. Motivation - Statistic
From the graph you can see that almost 90% of path are non-critical.
From this graph, we can determine whether voltage separation is necessary (by Amdahl’s Law)
Number of paths (normalied)
Path-delay(normalized) 4
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F08 ECE/CS 6710 Digital VLSI Design

5. Drawback of Multi-Voltage
Low voltage output can not drive the high voltage input directly.
Therefore, there is a classic example of voltage interface driving low to high.
However, this suffers power and performance.
Significant static power dissipation is therefore generated during the time Outl is high. A small P5, however, affects the low-to-high transition of Out2, increasing this transition time. 5
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F08 ECE/CS 6710 Digital VLSI Design

6. Latest Voltage Interface
ISCA 2002 – CMOS Voltage Interface, Kursun et al. 6
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F08 ECE/CS 6710 Digital VLSI Design

7. F08 ECE/CS 6710 Digital VLSI Design
Our Goals and Plans
We have this global goal, because we would like to try other power-saving techniques if we have more time.
Global Goal: Design a low power MIPS processor.
Project Goal: Implement multiple voltage MIPS processor
Plan 1: Figure out a critical path on baseline MIPS processor
Plan 2: Figure out the range of the maximum non-critical modules
Plan 3: Make an efficient voltage interface cell.
Plan 4: Figure out the range that uses minimum voltage interfaces
Plan 5: Make an efficient floor planning
Plan 6: Make a multiple voltage MIPS processor
Plan 7: Test and comparison
No pipeline, No-FP, No-memory unit
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F08 ECE/CS 6710 Digital VLSI Design

8. Multiple Voltage MIPS uP Design (II)
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F08 ECE/CS 6710 Digital VLSI Design

9. Multiple Voltage MIPS uP Design (I)
Later we will figure out non-critical path within critical modules.
Multiple Voltage MIPS uP Design (I)
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F08 ECE/CS 6710 Digital VLSI Design

10. Floor Planning on Multiple-Voltage
VDDH and VDDL cells should be separated because their N-well voltages are different. There are several voltage separation schemes:
a. row-interleaved b. row-split c. voltage island
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F08 ECE/CS 6710 Digital VLSI Design

11. End of the Presentation
Questions?
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F08 ECE/CS 6710 Digital VLSI Design