Presentation is loading. Please wait.

Presentation is loading. Please wait.

Computer System Design (Processor Design)

Published byKelley Hancock Modified over 6 years ago

Similar presentations

Presentation on theme: "Computer System Design (Processor Design)"— Presentation transcript:

1 Computer System Design (Processor Design)
Lecture 10 : Memory Technology CE Suntiamorntut 2/1999

2 Where are we now? CE Suntiamorntut 2/1999

3 Technology Trends CE Suntiamorntut 2/1999

4 Expanded View of the Memory System
CE Suntiamorntut 2/1999

5 Memory Hierarchy of a Modern Computer System
CE Suntiamorntut 2/1999

6 How is the hierarchy managed?
CE Suntiamorntut 2/1999

7 Logic Diagram of a Typical SRAM
CE Suntiamorntut 2/1999

8 Typical of SRAM Timing CE Suntiamorntut 2/1999

9 Classical DRAM Organization (square)
CE Suntiamorntut 2/1999

10 Logical Diagram of a Typical DRAM
CE Suntiamorntut 2/1999

11 Art of Memory System Design
CE Suntiamorntut 2/1999

12 Example : 1 KB Direct Mapped Cache with 32 B Blocks
CE Suntiamorntut 2/1999

13 Example : Fully Associative
CE Suntiamorntut 2/1999

14 A Two-way Set Associative Cache
CE Suntiamorntut 2/1999

15 Disadvantage of Set Associative Cache
CE Suntiamorntut 2/1999

16 How do you design a cache ?
CE Suntiamorntut 2/1999

17 1 KB Direct mapped Cache, 32B blocks
CE Suntiamorntut 2/1999

18 Improving Cache Performance : 3 general options
CE Suntiamorntut 2/1999

19 Where can a block be placed in the upper level?
CE Suntiamorntut 2/1999

20 Example CE Suntiamorntut 2/1999

Download ppt "Computer System Design (Processor Design)"

Similar presentations

361 Computer Architecture Lecture 15: Cache Memory

361 Computer Architecture Lecture 15: Cache Memory
Cache Performance 1 Computer Organization II ©2005-2013 CS:APP & McQuain Cache Memory and Performance Many of the following slides are taken with.

Cache Performance 1 Computer Organization II © CS:APP & McQuain Cache Memory and Performance Many of the following slides are taken with.
Cache Heng Sovannarith

Cache Heng Sovannarith
5-1 Memory System. Logical Memory Map. Each location size is one byte (Byte Addressable) Logical Memory Map. Each location size is one byte (Byte Addressable)

5-1 Memory System. Logical Memory Map. Each location size is one byte (Byte Addressable) Logical Memory Map. Each location size is one byte (Byte Addressable)
Caching IV Andreas Klappenecker CPSC321 Computer Architecture.

Caching IV Andreas Klappenecker CPSC321 Computer Architecture.
1 Lecture 20 – Caching and Virtual Memory  2004 Morgan Kaufmann Publishers Lecture 20 Caches and Virtual Memory.

1 Lecture 20 – Caching and Virtual Memory  2004 Morgan Kaufmann Publishers Lecture 20 Caches and Virtual Memory.
1 Lecture 16B Memories. 2 Memories in General Computers have mostly RAM ROM (or equivalent) needed to boot ROM is in same class as Programmable Logic.

1 Lecture 16B Memories. 2 Memories in General Computers have mostly RAM ROM (or equivalent) needed to boot ROM is in same class as Programmable Logic.
The Memory Hierarchy II CPSC 321 Andreas Klappenecker.

The Memory Hierarchy II CPSC 321 Andreas Klappenecker.
CIS429.00-13.1 °The Five Classic Components of a Computer °Today’s Topics: Memory Hierarchy Cache Basics Cache Exercise (Many of this topic’s slides were.

CIS °The Five Classic Components of a Computer °Today’s Topics: Memory Hierarchy Cache Basics Cache Exercise (Many of this topic’s slides were.
Memory Organization.

Memory Organization.
Caching I Andreas Klappenecker CPSC321 Computer Architecture.

Caching I Andreas Klappenecker CPSC321 Computer Architecture.
EECS 318 CAD Computer Aided Design LECTURE 10: Improving Memory Access: Direct and Spatial caches Instructor: Francis G. Wolff Case.

EECS 318 CAD Computer Aided Design LECTURE 10: Improving Memory Access: Direct and Spatial caches Instructor: Francis G. Wolff Case.
Lecture 14 Memory Hierarchy and Cache Design Prof. Mike Schulte Computer Architecture ECE 201.

Lecture 14 Memory Hierarchy and Cache Design Prof. Mike Schulte Computer Architecture ECE 201.
1 Memory Hierarchy The main memory occupies a central position by being able to communicate directly with the CPU and with auxiliary memory devices through.

1 Memory Hierarchy The main memory occupies a central position by being able to communicate directly with the CPU and with auxiliary memory devices through.
1 Virtual Memory Main memory can act as a cache for the secondary storage (disk) Advantages: –illusion of having more physical memory –program relocation.

1 Virtual Memory Main memory can act as a cache for the secondary storage (disk) Advantages: –illusion of having more physical memory –program relocation.
1  1998 Morgan Kaufmann Publishers Recap: Memory Hierarchy of a Modern Computer System By taking advantage of the principle of locality: –Present the.

1  1998 Morgan Kaufmann Publishers Recap: Memory Hierarchy of a Modern Computer System By taking advantage of the principle of locality: –Present the.
ECE 424 Embedded Systems Design Lecture 5: Platform Architecture Ning Weng.

ECE 424 Embedded Systems Design Lecture 5: Platform Architecture Ning Weng.
The Goal: illusion of large, fast, cheap memory Fact: Large memories are slow, fast memories are small How do we create a memory that is large, cheap and.

The Goal: illusion of large, fast, cheap memory Fact: Large memories are slow, fast memories are small How do we create a memory that is large, cheap and.
1 Chapter Seven. 2 Users want large and fast memories! SRAM access times are 2 - 25ns at cost of $100 to $250 per Mbyte. DRAM access times are 60-120ns.

1 Chapter Seven. 2 Users want large and fast memories! SRAM access times are ns at cost of $100 to $250 per Mbyte. DRAM access times are ns.
1 Chapter Seven. 2 Users want large and fast memories! SRAM access times are 2 - 25ns at cost of $100 to $250 per Mbyte. DRAM access times are 60-120ns.

1 Chapter Seven. 2 Users want large and fast memories! SRAM access times are ns at cost of $100 to $250 per Mbyte. DRAM access times are ns.

Similar presentations

Ads by Google