1. NA61 - Single Computer DAQ !FE MB
24 x CB
DDL
32x FE MB
optical cables
existing
flat ribbon
cables
Serial LVDS link
STP cables 8x 8x
5 700 x !!
248 x CB
DDL MB FE 1x
5 600 x 32-channel ADC front-end digitizer cards
vs.
1x DAQ Server PC !!
w/ 4x 2-ch DDL Read-out Receiver Cards (PCI Express RORC)
Max. aggregate data throughput: ~ 1500 MB/s

2. NA61 DAQ architecture Trigger box 5 700 x FE cards (A/D converters) FEMB MB MB
240 x Read-out Motherboards
32x
BUSY CB 8x CB
8 x Concentrator Boxes
Configuration Data
8 x 2 Gb/s Detector Data Link (DDL)
Event Fragments
RORC
4 Read-Out Receiver Cards (RORC)
RORC
RORC
RORC
1 DAQ PC
1 single DAQ Server PC
MONITORING
DATA STORAGE

3. DDL (2.5 Gb/s optical link)
Concentrator
FIFO
MULTIPLEXER
32-bits
Custom Serial link (48 Mb/s LVDS)
Motherboards 1 2 i
i+1 23 24
PED
THRE
HUFF
  ZERO suppression  
FIFO 1 2 i
i+1 23 24
PED
THRE
HUFF
  ZERO suppression  
FIFO
Huffman code table
FIFO
Huffman code table
8-bits
8-bits
Pedestal tables
HUFF
Pedestal tables
24 x 32 x 8-bits
24 x 32 x 8-bits
  ZERO suppression  
8-bits
8-bits
PED
THRE
PED
THRE
PED
THRE
PED
THRE
PED
THRE
PED
THRE
9-bits
9-bits FE
cards 1 2 i
i+1 23 24 FE
cards

4. NA61 MotherBoard Block Diagram
FE Connector 1A
FE Connector 2A
FE Connector 3A
FE Connector 12A
FE Connector 1B
FE Connector 2B
FE Connector 3B
FE Connector 12B
FE Address [5..0]
FE Clocks
FE Read-Out Control Signals
FE Diagnostic Signals
D3A[8..0]D3B[8..0]
Cyclone II FPGA
EP2C35F672
D12A[8..0] D12B[8..0]
SRAM 16 x 64k
D2A[8..0] D2B[8..0]
D1A[8..0] D1B[8..0]
SRAM 16 x 64k
D1[15..0] D2[15..0] D3[15..0] D4[15..0] A[15..0]
System Clock
SRAM 16 x 64k
FE & MB Power Monitor Circuits
SRAM 16 x 64k
Config. EPROM (user)
FPGA Config. CPLD
Voltage Regulators
Config EPROM (factory)
FE Power Supply Connector
MB Power Supply Connector
Config. Connector
Clock & Trigger Connector
Jumpers, LEDs
LVDS Link Connector
Busy Connector 4

5. FPGA Signals FE Signals Connection to Connector Board Others
24*9 bit paralell data bus (216 Inputs)
Adress bus (6 Outputs)
Clocks: ADC_CLK, SCA_CLK (4 Outputs)
Read out control signals (9 Outputs)
Diagnostic signals (6 Outputs)
Connection to Connector Board
LVDS signals to Concentrator (2 Inputs, 2 Outputs)
Others
Power monitor data (8 Input)
Power monitor control (7 Outputs, 1 Input)
Jumpers (13 Input)
LEDs and Test points (5 Outputs)

6. NA61 Read-out MotherBoard Timing
Write: 41us (512*80ns)
Read: 23,5ms ((5,6us+10us+20us+10,2us)*512)
Analog Reset 10us
Set Ampl. 10us
Analog to Digital Conv. 20us (256 ADC cycles)
Read Card 1-2 2*5,1us
Analog Reset 5,6us
Set Ampl. 10us
Analog to Digital Conv. 20us (256 ADC cycles)
PA_Enable/Reset
Write/Read
Reset_Shift_Reg
Analog_Reset
SCA_CLK (512 cycles)
ADC_Reset
ADC_Load_Buffer
ADC_OE1
ADC_OE2
Connector 1
1.Data Out
2.Data Out
Connector 2
1.Data Out
2.Data Out
Connector 24
1.Data Out
2.Data Out
ADC_CLK

7. Data Flow in Read-out MB
To the Concentrator Box
FIFO
8 bit
Pad-row Builder
Pedestal Table
Zero Suppression
8 bit
Multiplexer
8 bit
Threshold
Threshold
Threshold
Threshold
8 bit
8 bit - - - -
9 bit
FE 1
FE 2
FE 23
FE 24

8. NA61 MB FW Simplified Block Diagram
FE Write and Read-out Controller
Pad-Row Builder
Zero Compression
Status, Data, Event Builder and Serialiser
FE Data [215..0]
FE Address [5..0]
FE Read-Out Control Signals
Serial CLK
Serial Data
Data[7..0]
Data[8..0]
Data[191..0]
Write/Read
Pedestal [191..0]
Data[191..0]
Data[7..0]
Config. EPROM
External RAM (4x1Mbit)
Pedestal (Data) Write and Read-out Controller
Deserialiser and Command, Status, Data decoder
D[63..0]
A[15..0]
R/W
Upload Pedestal Data[8..0]
Download Pedestal Data[32..0]
Serial CLK
Serial Data

9. NA61 ConcentratorBox Block Diagram
LVDS Connector Channel 1
LVDS Connector Channel 3
LVDS Connector Channel 5
LVDS Connector Channel 7
LVDS Connector Channel 31
LVDS Connector Channel 2
LVDS Connector Channel 4
LVDS Connector Channel 6
LVDS Connector Channel 8
LVDS Connector Channel 32
Ch 15 – 32
Ch 1 – 8
DDL SIU
Optical link
Actel
DDL Controls
DDL Clock
DDL Data
LVDS Transceiver (Ch 1 – 8)
LVDS Receiver (Ch 1 – 8)
Cyclone II FPGA
EP2C20F484
System Clock
Serial Data & Clock In (Ch 1..8)
Serial Data & Clock Out (Ch 1..8)
Config. EPROM
Voltage Regulators
Power Connector
Busy Connector
Config. Connector

10. MotherBoard Data Structure
Status (20 x 8 bit)
(n x 8 bit)
Data
(4 x 8 bit)
Header
Jumper Settings [31..18]
Sending Status[17..15]
Trigger Counter [14..0]
Front-End (1-4) Voltages [31..0]
Front-End (5-8) Voltages [31..0]
Front-End (9-12) Voltages [31..0]
MotherBoard Voltages [31..0]
MotherBoard Error Status [31..0]